From 70645de004b8f14f29059f33575a1c1cab48e79b Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Wed, 14 Jan 2009 09:36:50 +0000
Subject: [PATCH] - uses common fixed_pkg

git-svn-id: http://moon:8086/svn/vhdl/trunk@239 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/radio/mix/src/tb_undc_real.vhd | 15 +++++++++------
 lib/radio/mix/src/undc_real.vhd    | 22 +++++++++++++---------
 2 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd
index 3c7a52f..3fc872b 100644
--- a/lib/radio/mix/src/tb_undc_real.vhd
+++ b/lib/radio/mix/src/tb_undc_real.vhd
@@ -17,9 +17,12 @@ use IEEE.MATH_REAL.ALL;
 USE ieee.numeric_std.ALL;
 use std.textio.all; --  Imports the standard textio package.
 
+library ieee_proposed;
+use ieee_proposed.math_utility_pkg.all;
+use ieee_proposed.fixed_pkg.all;
+
 library work;
-use work.fixed_pkg.all;
-use work.mix_pkg.all;
+use work.fixed_util_pkg.all;
 use work.PCK_FIO.all;
 
 ENTITY tb_undc_real IS
@@ -29,8 +32,8 @@ ENTITY tb_undc_real IS
 		nbits_k			: integer := 24;
 		nbits_k_frac	: integer := 24;
 		has_in_reg		: boolean := true;
-		rounding		: boolean := true;
-		saturating		: boolean := true
+		rounding		: fixed_round_style_type := fixed_round;
+		saturating		: fixed_overflow_style_type := fixed_saturate
         );
 END tb_undc_real;
 
@@ -45,8 +48,8 @@ ARCHITECTURE behavior OF tb_undc_real IS
 		nbits_k			: integer;
 		nbits_k_frac	: integer;
 		has_in_reg		: boolean;
-		rounding		: boolean;
-		saturating		: boolean
+		rounding		: fixed_round_style_type;
+		saturating		: fixed_overflow_style_type
 	);
 	Port
 	(
diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd
index be6df6e..e4a3bba 100644
--- a/lib/radio/mix/src/undc_real.vhd
+++ b/lib/radio/mix/src/undc_real.vhd
@@ -21,8 +21,12 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.MATH_REAL.ALL;
 USE ieee.numeric_std.ALL;
-use work.fixed_pkg.all;
-use work.mix_pkg.all;
+
+library ieee_proposed;
+use ieee_proposed.math_utility_pkg.all;
+use ieee_proposed.fixed_pkg.all;
+
+use work.fixed_util_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
@@ -36,8 +40,8 @@ Generic
 	nbits_k			: integer := 12;
 	nbits_k_frac	: integer := 12;
 	has_in_reg		: boolean := false;
-	rounding		: boolean := true;
-	saturating		: boolean := true
+	rounding		: fixed_round_style_type := fixed_round;
+	saturating		: fixed_overflow_style_type := fixed_saturate
 );
 Port
 (
@@ -67,8 +71,8 @@ signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sprot
 
 begin
 
-dout <= resize(y, sproto(nbits_data, nbits_data_frac), rounding, saturating);
-dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false);
+dout <= resize(y, sproto(nbits_data, nbits_data_frac), saturating, rounding);
+dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), fixed_wrap, fixed_truncate);
 
 ------------------------------------------------------------
 	proc_din_reg: process(clk, din_valid, din)
@@ -121,7 +125,7 @@ dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false);
 ------------------------------------------------------------
 	proc_pipe_y: process(clk, x, dc)
 	begin
-		y <= resize(x - dc, y, false, false);
+		y <= resize(x - dc, y, fixed_wrap, fixed_truncate);
 		if rising_edge(clk) then
 			if srst = '1' then
 				y1 <= to_sfixed(0, y1);
@@ -129,8 +133,8 @@ dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false);
 				dc <= to_sfixed(0, dc);
 			else
 				y1 <= y;
-				y2 <= resize(y1 * k, y2, false, false);
-				dc <= resize(y2 + dc, dc, false, false);
+				y2 <= resize(y1 * k, y2, fixed_wrap, fixed_truncate);
+				dc <= resize(y2 + dc, dc, fixed_wrap, fixed_truncate);
 			end if;	
 		end if;	
 	end process;