From 6f74cd16628cc51d847fc5f738aad942f73325d5 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 6 May 2009 21:35:03 +0000 Subject: [PATCH] - removed register output latch (latch introduced global clock buffer, which is deprecated) - CPU is configured as BIG-endian Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@474 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/tb_mips_top.vhd | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 52b7f53..5f89946 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -46,7 +46,7 @@ ARCHITECTURE behavior OF tb_mips_top IS -- Master signal rst : STD_LOGIC := '1'; signal clk : STD_LOGIC := '0'; - signal eb : STD_LOGIC := '0'; + signal eb : STD_LOGIC := '1'; signal ACK_I : STD_LOGIC := '0'; signal SRDY_I : STD_LOGIC := '0'; signal ADDR_O : unsigned(31 downto 0); @@ -103,7 +103,7 @@ ARCHITECTURE behavior OF tb_mips_top IS signal gpi1 : unsigned(31 downto 0) := (others => '0'); signal int_timer : std_logic; - signal int_uart_rx : std_logic; + signal int_uart : std_logic; signal rx : std_logic := '1'; signal tx : std_logic; @@ -216,7 +216,7 @@ uut: entity work.mips_top MRDY_O => MRDY_O, INT => INT ); - INT(1) <= int_uart_rx; + INT(1) <= int_uart; INT(5) <= int_timer; inst_rom : entity work.rom_wb @@ -333,8 +333,7 @@ inst_uart : entity work.uart_wb ADDR_I => ADDR_O, DAT_I => DAT_O, DAT_O => DAT_O_uart, - INT_RX_O => int_uart_rx, - INT_TX_O => open, + INT_O => int_uart, ser_rx => rx, ser_tx => tx ); @@ -387,7 +386,7 @@ SRAM_WRITE: FLASH_READ: process(rst, flash_cs_n, flash_oe_n, flash_a) type file_t is file of integer; - file load_flash : file_t open read_mode is "test_endianess.flash.bin"; + file load_flash : file_t open read_mode is "hello.flash.bin"; variable instr : integer; variable index : natural; variable temp : signed(31 downto 0);