Initial version

Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@575 cc03376c-175c-47c8-b038-4cd826a8556b
2009-11-03 12:59:40 +00:00
parent 76ef050e55
commit 6f27bf0c89
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+-------------------------------------------------------------------------
+-- Project: MIPS System controller
+-- This file: 
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.async_types.all;
+
+package async_defs is
+
+	constant ts_flash : async_timespec_t :=
+	(
+		ncyc_leadin				=> 1,
+		ncyc_pulse_rd			=> 12,
+		ncyc_pulse_wr			=> 7,
+		ncyc_leadout			=> 1,
+		ncyc_release			=> 4,
+		ncyc_pulse_rst			=> 8,
+		can_page_rd				=> true,
+		nbits_page_rd			=> 4,
+		ncyc_pulse_page_rd		=> 3,
+		pol_cs					=> '1',
+		pol_oe					=> '0',
+		pol_we					=> '0',
+		pol_be					=> '0',
+		pol_rst					=> '0'
+	);
+
+	constant ts_usb : async_timespec_t :=
+	(
+		ncyc_leadin				=> 1,
+		ncyc_pulse_rd			=> 6,
+		ncyc_pulse_wr			=> 6,
+		ncyc_leadout			=> 1,
+		ncyc_release			=> 8,
+		ncyc_pulse_rst			=> 8,
+		can_page_rd				=> false,
+		nbits_page_rd			=> 0,
+		ncyc_pulse_page_rd		=> 0,
+		pol_cs					=> '0',
+		pol_oe					=> '0',
+		pol_we					=> '0',
+		pol_be					=> '0',
+		pol_rst					=> '0'
+	);
+
+	----------------------------------------------------------------------------------------------
+	
+end async_defs;