Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@24 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,487 @@
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-------------------------------------------------------------------------
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-- Project: SDRAM controller
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-- This file: SDRAM main controller and user I/F
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.sdram_config.all;
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use work.sdram_types.all;
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use work.utils_pkg.all;
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entity sdram_ctrl is
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Generic
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(
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f_sysclk : natural := 100E6;
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BL : natural := 2
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);
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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u_busy : out STD_LOGIC;
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u_tag_in : in user_tag_t;
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u_tag_out : out user_tag_t;
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u_addr : in user_addr_t;
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u_cmd : in user_cmd_t;
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u_cmd_we : in STD_LOGIC;
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col_addr : out col_addr_t;
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sdr_cmd_busy : in STD_LOGIC;
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sdr_cmd : out sdr_cmd_t;
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sdr_cmd_we : out STD_LOGIC;
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sdr_mode : out mode_word_t;
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sdr_cke : out STD_LOGIC
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);
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end sdram_ctrl;
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architecture behaviour of sdram_ctrl is
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constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
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type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
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signal st_ctrl, st_ctrl_next : ctrl_state_t;
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constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
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signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
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signal pwr_up_cnt_rst : std_logic;
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signal pwr_up_finished : std_logic;
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signal cycle_cnt : natural range 0 to 255;
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signal cc_preset : natural range 0 to 255;
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signal cc_load_en : std_logic;
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signal cycle_finished : std_logic;
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signal seq_cnt : natural range 0 to 31;
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signal seq_rst_en : std_logic;
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signal seq_cnt_en : std_logic;
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constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
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signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
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signal refresh_request : std_logic;
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signal refresh_cnt_rst : std_logic;
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signal addr_reg_load_en : std_logic;
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signal u_tag_reg : user_tag_t;
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signal bank_addr_reg : bank_addr_t;
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signal row_addr_reg : row_addr_t;
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signal col_addr_reg : col_addr_t;
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signal u_bank_addr : bank_addr_t;
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signal u_row_addr : row_addr_t;
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signal u_col_addr : col_addr_t;
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signal act_request : std_logic;
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signal act_request_set : std_logic;
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signal act_request_clr : std_logic;
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type init_seq_rom_t is array (0 to 14) of init_seq_t;
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constant init_seq_rom : init_seq_rom_t :=
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(
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_PRE,
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mode_word => "000010000000000",
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wait_cycle => 0
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_LMR,
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mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
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wait_cycle => 0
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_LMR,
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mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
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wait_cycle => 200
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_PRE,
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mode_word => "000010000000000",
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wait_cycle => 0
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_AR,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_AR,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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),
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(
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cmd => SD_LMR,
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mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
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wait_cycle => 200
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),
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(
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cmd => SD_NOP,
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mode_word => (others => '0'),
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wait_cycle => 0
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)
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);
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begin
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u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
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u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
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u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
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------------------------------------------------------------------------------------------
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fsm_ctrl_state:
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process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
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begin
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u_busy <= '1';
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pwr_up_cnt_rst <= '0';
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cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
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cc_load_en <= '0';
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sdr_cmd <= init_seq_rom(seq_cnt).cmd;
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sdr_cmd_we <= '0';
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sdr_mode <= bank_addr_reg & row_addr_reg;
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col_addr <= col_addr_reg;
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sdr_cke <= '1';
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seq_cnt_en <= '0';
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seq_rst_en <= '0';
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addr_reg_load_en <= '0';
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refresh_cnt_rst <= '0';
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act_request_set <= '0';
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act_request_clr <= '0';
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u_tag_out <= u_tag_reg;
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st_ctrl_next <= st_ctrl;
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case st_ctrl is
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when RESET =>
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sdr_cke <= '0';
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pwr_up_cnt_rst <= '1';
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st_ctrl_next <= POWER_WAIT;
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when POWER_WAIT =>
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sdr_cke <= '0';
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if pwr_up_finished = '1' then
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seq_rst_en <= '1';
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st_ctrl_next <= INIT;
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end if;
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when INIT =>
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sdr_mode <= init_seq_rom(seq_cnt).mode_word;
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sdr_cmd <= init_seq_rom(seq_cnt).cmd;
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cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
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if seq_cnt = init_seq_rom_t'high then
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act_request_set <= '1';
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refresh_cnt_rst <= '1';
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st_ctrl_next <= USER_READY;
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elsif sdr_cmd_busy = '0' then
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cc_load_en <= '1';
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sdr_cmd_we <= '1';
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st_ctrl_next <= INIT_WAIT;
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end if;
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when INIT_WAIT =>
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if sdr_cmd_busy = '0' and cycle_finished = '1' then
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seq_cnt_en <= '1';
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st_ctrl_next <= INIT;
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end if;
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when USER_READY =>
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if sdr_cmd_busy = '0' then
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if refresh_request = '1' then
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sdr_mode(BIT_PRE_ALL) <= '1';
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sdr_cmd_we <= '1';
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sdr_cmd <= SD_PRE;
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st_ctrl_next <= REFRESH;
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else
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u_busy <= '0';
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if u_cmd_we = '1' then
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case u_cmd is
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when UCMD_NOP =>
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sdr_cmd <= SD_NOP;
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when UCMD_LMR =>
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sdr_cmd <= SD_NOP;
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when UCMD_WRITE =>
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col_addr <= u_col_addr;
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u_tag_out <= u_tag_in;
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sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
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addr_reg_load_en <= '1';
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act_request_clr <= '1';
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sdr_cmd <= SD_WRITE;
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if (u_row_addr /= row_addr_reg) or act_request = '1' then
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st_ctrl_next <= USER_WRITE_PRE;
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elsif (u_bank_addr /= bank_addr_reg) then
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if ENABLE_PRE_ALL = '1' then
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st_ctrl_next <= USER_WRITE_ACT;
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else
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st_ctrl_next <= USER_WRITE_PRE;
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end if;
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elsif sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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else
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st_ctrl_next <= USER_WRITE;
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end if;
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when UCMD_READ =>
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col_addr <= u_col_addr;
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u_tag_out <= u_tag_in;
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sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
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addr_reg_load_en <= '1';
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act_request_clr <= '1';
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sdr_cmd <= SD_READ;
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if (u_row_addr /= row_addr_reg) or act_request = '1' then
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st_ctrl_next <= USER_READ_PRE;
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elsif (u_bank_addr /= bank_addr_reg) then
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if ENABLE_PRE_ALL = '1' then
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st_ctrl_next <= USER_READ_ACT;
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else
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st_ctrl_next <= USER_READ_PRE;
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end if;
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elsif sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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else
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st_ctrl_next <= USER_READ;
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end if;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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when USER_WRITE_PRE =>
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sdr_cmd <= SD_PRE;
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sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_WRITE_ACT;
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end if;
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when USER_WRITE_ACT =>
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sdr_cmd <= SD_ACT;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_WRITE;
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end if;
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when USER_WRITE =>
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sdr_cmd <= SD_WRITE;
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sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_READY;
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end if;
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when USER_READ_PRE =>
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sdr_cmd <= SD_PRE;
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sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_READ_ACT;
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end if;
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when USER_READ_ACT =>
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sdr_cmd <= SD_ACT;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_READ;
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end if;
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when USER_READ =>
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sdr_cmd <= SD_READ;
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sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_READY;
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end if;
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when REFRESH =>
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sdr_cmd <= SD_AR;
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if sdr_cmd_busy = '0' then
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sdr_cmd_we <= '1';
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st_ctrl_next <= USER_READY;
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refresh_cnt_rst <= '1';
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act_request_set <= '1';
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end if;
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when others =>
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st_ctrl_next <= RESET;
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end case;
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end process;
|
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|
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fsm_ctrl_state_next:
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process (rst, clk)
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begin
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if rst = '1' then
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st_ctrl <= RESET;
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elsif rising_edge(clk) then
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st_ctrl <= st_ctrl_next;
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end if;
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end process;
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------------------------------------------------------------------------------------------
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act_request_register:
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process (rst, clk)
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begin
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if rst = '1' then
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act_request <= '1';
|
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elsif rising_edge(clk) then
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if act_request_set = '1' then
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act_request <= '1';
|
||||
elsif act_request_clr = '1' then
|
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act_request <= '0';
|
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end if;
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||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
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user_addr_register:
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process (rst, clk)
|
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begin
|
||||
if rst = '1' then
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bank_addr_reg <= (others => '0');
|
||||
row_addr_reg <= (others => '0');
|
||||
col_addr_reg <= (others => '0');
|
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u_tag_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if addr_reg_load_en = '1' then
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||||
bank_addr_reg <= u_bank_addr;
|
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row_addr_reg <= u_row_addr;
|
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col_addr_reg <= u_col_addr;
|
||||
u_tag_reg <= u_tag_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
power_up_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
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pwr_up_cnt <= 0;
|
||||
pwr_up_finished <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
pwr_up_finished <= '0';
|
||||
if pwr_up_cnt_rst = '1' then
|
||||
pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
|
||||
else
|
||||
if pwr_up_cnt /= 0 then
|
||||
pwr_up_cnt <= pwr_up_cnt - 1;
|
||||
else
|
||||
pwr_up_finished <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
refresh_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
refresh_cnt <= 0;
|
||||
refresh_request <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
refresh_request <= '0';
|
||||
if refresh_cnt_rst = '1' then
|
||||
refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
|
||||
else
|
||||
if refresh_cnt /= 0 then
|
||||
refresh_cnt <= refresh_cnt - 1;
|
||||
else
|
||||
refresh_request <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
cycle_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cycle_cnt <= 0;
|
||||
cycle_finished <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
cycle_finished <= '0';
|
||||
if cc_load_en = '1' then
|
||||
cycle_cnt <= cc_preset;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
else
|
||||
cycle_finished <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
seq_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
seq_cnt <= 0;
|
||||
elsif rising_edge(clk) then
|
||||
if seq_rst_en = '1' then
|
||||
seq_cnt <= 0;
|
||||
elsif seq_cnt_en = '1' then
|
||||
if seq_cnt /= init_seq_rom_t'high then
|
||||
seq_cnt <= seq_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
end behaviour;
|
||||
Reference in New Issue
Block a user