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- added generic for fractional number of bits

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git-svn-id: http://moon:8086/svn/vhdl/trunk@149 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-22 09:57:01 +00:00
parent 4bb7087b60
commit 6e65134b53
1 changed files with 33 additions and 26 deletions
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lib/radio/nco/src/tb_mix_cordic.vhd
+33 -26
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@@ -27,7 +27,7 @@ ENTITY tb_mix IS
Generic
(
nbits_wave_in : integer := 16;
nbits_wave_out : integer := 16;
nbits_wave_out : integer := 18;
nbits_phase : integer := 20
);
END tb_mix;
@@ -38,25 +38,27 @@ ARCHITECTURE behavior OF tb_mix IS
COMPONENT mix
GENERIC
(
nbits_wave_in : integer;
nbits_wave_out : integer;
nbits_phase : integer
nbits_wave_in : integer;
nbits_wave_in_frac : integer;
nbits_wave_out : integer;
nbits_wave_out_frac : integer;
nbits_phase : integer
);
PORT(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
wave_in_i : in sfixed;
wave_in_q : in sfixed;
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic;
debug_out : out debug_mix_out_t
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
wave_in_i : in sfixed;
wave_in_q : in sfixed;
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic;
debug_out : out debug_mix_out_t
);
END COMPONENT;
@@ -65,6 +67,7 @@ ARCHITECTURE behavior OF tb_mix IS
GENERIC
(
nbits_wave : integer;
nbits_wave_frac : integer;
nbits_phase : integer
);
PORT(
@@ -92,8 +95,8 @@ ARCHITECTURE behavior OF tb_mix IS
constant PERIOD : time := 10 ns;
constant num_steps : integer := 1000000;
constant nbits_wave_in_frac : integer := nbits_wave_in;
constant nbits_wave_out_frac : integer := nbits_wave_out;
constant nbits_wave_in_frac : integer := nbits_wave_in-2;
constant nbits_wave_out_frac : integer := nbits_wave_out-2;
SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_phase);
SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
@@ -125,8 +128,8 @@ ARCHITECTURE behavior OF tb_mix IS
SIGNAL rfgen_phase_in : unsigned(nbits_phase-1 downto 0);
--Outputs
SIGNAL rfgen_wave_out_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
SIGNAL rfgen_wave_out_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
SIGNAL rfgen_wave_out_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL rfgen_wave_out_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL rfgen_out_valid : std_logic;
SIGNAL rfgen_debug_out : debug_out_t;
SIGNAL fileout_enable : std_logic := '0';
@@ -137,9 +140,11 @@ BEGIN
uut: mix
GENERIC MAP
(
nbits_wave_in => nbits_wave_in,
nbits_wave_out => nbits_wave_out,
nbits_phase => nbits_phase
nbits_wave_in => nbits_wave_in,
nbits_wave_in_frac => nbits_wave_in_frac,
nbits_wave_out => nbits_wave_out,
nbits_wave_out_frac => nbits_wave_out_frac,
nbits_phase => nbits_phase
)
PORT MAP
(
@@ -163,6 +168,7 @@ BEGIN
GENERIC MAP
(
nbits_wave => nbits_wave_in,
nbits_wave_frac => nbits_wave_in_frac,
nbits_phase => nbits_phase
)
PORT MAP
@@ -188,7 +194,8 @@ BEGIN
wait for PERIOD/2;
END PROCESS;
wave_in_i <= resize(0.25*rfgen_wave_out_i, wave_in_i, false, true);
-- wave_in_i <= resize(1.0*rfgen_wave_out_i, wave_in_i, false, true);
wave_in_i <= rfgen_wave_out_i;
wave_in_q <= to_sfixed(0.0, wave_in_q);
tb : PROCESS