diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo
index 1f1298b..5d6a5bb 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.fdo
@@ -2,7 +2,14 @@
 ##
 vlib work
 
+# Packages
+vcom -explicit  -93 "../src/core/TLB/mips_util_pkg.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_types.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../JBUS/src/busmaster_types.vhd"
+
 # RAMS
+vcom -explicit  -93 "../../../rams/dpram_1w1r1wc_sim.vhd"
 vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
 vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
 vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
@@ -34,27 +41,33 @@ vcom -explicit  -93 "../../../misc/async_port_wb.vhd"
 vcom -explicit  -93 "../src/async_defs.vhd"
 
 # ROM
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
+vcom -explicit  -93 "../src/bootloader_flash.ROM.vhd"
 vcom -explicit  -93 "../../../misc/rom_wb.vhd"
 
 # MIPS
-vcom -explicit  -93 "../src/core/mips_types.vhd"
 vcom -explicit  -93 "../src/core/mips_instr.vhd"
 vcom -explicit  -93 "../src/core/mips_reg.vhd"
 vcom -explicit  -93 "../src/core/mips_shifter.vhd"
 vcom -explicit  -93 "../src/core/mips_alu.vhd"
 vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
-vcom -explicit  -93 "../src/core/mips_cop.vhd"
-vcom -explicit  -93 "../src/core/mips_icache.vhd"
-vcom -explicit  -93 "../src/core/mips_dcache.vhd"
-vcom -explicit  -93 "../src/core/mips_biu.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_cop.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_icache.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_dcache.vhd"
+#vcom -explicit  -93 "../src/core/TLB/mips_tlb_block.vhd"
+#vcom -explicit  -93 "../src/core/TLB/mips_tlb_20130811.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_cam.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_tlb_with_cam.vhd"
+#vcom -explicit  -93 "../src/core/TLB/mips_cam2.vhd"
+#vcom -explicit  -93 "../src/core/TLB/mips_tlb.vhd"
+vcom -explicit  -93 "../../../JBUS/src/busmaster_async.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_biu.vhd"
 vcom -explicit  -93 "../src/core/mips_bcu.vhd"
-vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
-vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_top.vhd"
 
-vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vcom -explicit  -93 "../src/tb_mips_top_tlb.vhd"
 vsim -t 1ps   -lib work tb_mips_top
-do {tb_mips_top.wdo}
+do {tb_mips_top_tlb.wdo}
 view wave
 view structure
 view signals
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
index 12b16c3..1d4de09 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
@@ -1,10 +1,12 @@
 onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate -divider {TOP interface}
+add wave -noupdate -format Literal /tb_mips_top/mem_area
 add wave -noupdate -format Logic /tb_mips_top/nmi
 add wave -noupdate -format Logic /tb_mips_top/rst
 add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/debug
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/debug
+add wave -noupdate -format Logic /tb_mips_top/cyc_o
 add wave -noupdate -format Logic /tb_mips_top/stb_o
 add wave -noupdate -format Logic /tb_mips_top/ack_i
 add wave -noupdate -format Logic /tb_mips_top/srdy_i
@@ -13,7 +15,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
 add wave -noupdate -format Logic /tb_mips_top/we_o
 add wave -noupdate -format Literal /tb_mips_top/sel_o
-add wave -noupdate -format Logic /tb_mips_top/cyc_o
 add wave -noupdate -format Logic /tb_mips_top/mrdy_o
 add wave -noupdate -format Literal /tb_mips_top/int
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_shifter/dout
@@ -21,56 +22,88 @@ add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst
 add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst
 add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run
 add wave -noupdate -divider BIU
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy
+add wave -noupdate -format Literal /tb_mips_top/mem_area
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_rdy
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_din
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_err
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_rdy
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_en
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_we
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_dout
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_addr
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/busy
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_re
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_full
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en
+add wave -noupdate -divider Busmaster
+add wave -noupdate -format Literal /tb_mips_top/mem_area
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/rst
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_cycle_finished
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_cycle_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_we
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/din
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/din_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/din_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/dout_vld
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/dout_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/rst_i
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/clk_i
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/ack_i
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/mdat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/addr_o
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/sel_o
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/we_o
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cyc_o
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/stb_o
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/mrdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_empty
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_empty
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cycle_busy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_read_en
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/read_cnt
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/jbus_cycle_busy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/jbus_state
 add wave -noupdate -divider {External components}
 add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal /tb_mips_top/mem_area
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi_0
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo_0
 add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
 add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
-add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_uart/uart_status_port
 add wave -noupdate -format Logic /tb_mips_top/rx
 add wave -noupdate -format Logic /tb_mips_top/tx
+add wave -noupdate -format Literal -radix ascii /tb_mips_top/inst_uart/reg_uart_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_uart/reg_uart_rx
+add wave -noupdate -divider SRAM
+add wave -noupdate -format Literal /tb_mips_top/mem_area
+add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
+add wave -noupdate -format Literal /tb_mips_top/sram_be_n
+add wave -noupdate -format Logic /tb_mips_top/sram_wr_n
+add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
+add wave -noupdate -divider FLASH
+add wave -noupdate -format Literal /tb_mips_top/mem_area
+add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
+add wave -noupdate -format Logic /tb_mips_top/flash_we_n
+add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
+add wave -noupdate -format Literal /tb_mips_top/flash_be_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
+add wave -noupdate -format Logic /tb_mips_top/flash_page_mode_en
 add wave -noupdate -divider {Interrupt Timer}
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp
@@ -82,8 +115,6 @@ add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack
 add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr
 add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/mem_area
 add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
 add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
 add wave -noupdate -format Logic /tb_mips_top/stb_o
@@ -115,7 +146,7 @@ add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s
 add wave -noupdate -divider ALU
 add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/sdu
+add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu
 add wave -noupdate -divider PC
 add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch
@@ -123,90 +154,292 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc
 add wave -noupdate -divider COP0
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dout
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/itlb_exc
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/dtlb_exc
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/tlb_sel
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/itlb_entry_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/itlb_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dtlb_entry_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dtlb_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/entry_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/entry_lo
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ex_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/regs
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/random
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/index
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state
 add wave -noupdate -divider Pipestages
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
+add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
+add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage.exc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.exc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/mem_stage
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/mem_stage.exc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/wb_stage
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/wb_stage.exc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ctrl_out
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
 add wave -noupdate -divider I-Cache
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_busy_state
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_ctrl_state
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/debug
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_va
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_pa
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/single_read_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/addr
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/single_read_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/single_read_set
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/read_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_req_rd
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tlb_query_out
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_icache/tlb_query_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/bus_din
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_din_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_din_vld
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_out
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cyc_complete
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_reg_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_wr
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_rd_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_wr
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/fill_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/fill_count_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/flush_count_rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/flush_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/flush_count_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/request_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/request_count_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/ram_read_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_all
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_ack
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_req
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_word_index
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/req_word_index
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram
+add wave -noupdate -divider I-TLB
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/ce
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_out
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/blk_hit
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/blk_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/pa
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/hit
+add wave -noupdate -divider I-TLB-CAM
 add wave -noupdate -divider D-Cache
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy_state
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cache_ctrl_state
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_data_avail
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_through_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_full
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/debug
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req_rd
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_va
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_pa
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/tlb_query_out
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/tlb_query_in
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_set
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/read_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/be
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_din
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_din_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_dout_vld
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_dout_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_out
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cyc_complete
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_rdy
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit_inv
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_reg_inv
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/data_ram_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/data_ram_dout
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/be_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_addr
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_we
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/data_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_dout_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_wr
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_all
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_ack
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_req
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_hit
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/ram_write_en
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_word_index
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/req_word_index
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/hit_cache_index
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_empty
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_data_avail
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/read_write_buffer
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_through_en
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_sel_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_data_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_addr_out
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_sel_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_data_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/ram
+add wave -noupdate -divider D-TLB
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/ce
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/query_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/query_out
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_d_tlb/blk_hit
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/blk_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/pa
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/hit
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_qry_entry_lo_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_qry_entry_lo_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_raddr
+add wave -noupdate -format Literal -label reg_entry_lo_mem -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/inst_reg_entry_lo/reg_mem
+add wave -noupdate -divider D-TLB-CAM
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clk_rd
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/tag_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/tag_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/hit
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/hit_vld
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/debug
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/state
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/state_next
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe0
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe3
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe0_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe1_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe2_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe3_rd
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/busy
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/vld_cam
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_addr_rd
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_addr
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_count_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/over_write
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {Cursor {5877623 ps} 0}
+WaveRestoreCursors {Cursor {1330548448 ps} 0}
 configure wave -namecolwidth 188
 configure wave -valuecolwidth 154
 configure wave -justifyvalue left
@@ -220,4 +453,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {5846736 ps} {5910641 ps}
+WaveRestoreZoom {1499841793 ps} {1500008327 ps}