diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
index 3108918..c5f3c9c 100644
--- a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
+++ b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
@@ -1,6 +1,8 @@
 ## NOTE:  Do not edit this file.
 ## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
 ##
+if {[file exists work]} {vdel -lib work -all}
+
 vlib work
 vcom -explicit  -93 "../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
index 1d8256e..edbf5d0 100644
--- a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
+++ b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
@@ -1,6 +1,8 @@
 ## NOTE:  Do not edit this file.
 ## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
 ##
+if {[file exists work]} {vdel -lib work -all}
+
 vlib work
 vcom -explicit  -93 "../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd
index f0cb6b8..69b300b 100644
--- a/lib/VGA_ctrl/src/char_gen.vhd
+++ b/lib/VGA_ctrl/src/char_gen.vhd
@@ -222,9 +222,8 @@ begin
 	PORT MAP(
 		clk_a		=> sys_clk,
 		clk_b		=> vga_clk,
-		en_a		=> '1',
-		en_b		=> '1',
 		we_a		=> a_ram_we,
+		re_b		=> '1',
 		addr_a		=> a_addr_wr,
 		addr_b		=> a_addr_rd,
 		din_a		=> a_data_wr,