diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo index cd32e25..ddbe21f 100644 --- a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo +++ b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo @@ -125,6 +125,7 @@ add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend6 add wave -noupdate -format Logic /tb_vga_frontend64/clk_o add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_x_next +add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_y_next add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_x add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_y add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_offset @@ -156,6 +157,7 @@ add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_fill_finish add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_x_next +add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_y_next add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_x add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_y add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_offset @@ -179,6 +181,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vg add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_dst add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_x_next +add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y_next add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_x add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_offset @@ -220,7 +223,7 @@ add wave -noupdate -format Logic /tb_vga_frontend64/clk_o add wave -noupdate -format Logic /tb_vga_frontend64/rst_o add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/read_reg TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {605145801 ps} 0} +WaveRestoreCursors {{Cursor 1} {604745488 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 118 configure wave -justifyvalue left @@ -234,4 +237,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {588909572 ps} {619583556 ps} +WaveRestoreZoom {0 ps} {2100 us} diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd index cd8135a..cdcb8bb 100644 --- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd @@ -569,12 +569,12 @@ STIMULUS: process reg_write(X"0000_0018", X"4000_0000"); -- set frontbuffer address reg_write(X"0000_001C", X"4000_0000"); -- set backbuffer address - reg_write(X"0000_0020", X"0000_0002"); -- set BLIT source address 0 - reg_write(X"0000_0028", X"0000_0002"); -- set BLIT source dimension 0 - reg_write(X"0000_0030", X"0000_0002"); -- set BLIT source address 1 - reg_write(X"0000_0038", X"0000_0002"); -- set BLIT source dimension 1 - reg_write(X"0000_0050", X"0000_0002"); -- set BLIT destination address - reg_write(X"0000_0058", X"0000_0002"); -- set BLIT destination dimension + reg_write(X"0000_0020", X"0000_0000"); -- set BLIT source address 0 + reg_write(X"0000_0024", X"0000_0000"); -- set BLIT source dimension 0 + reg_write(X"0000_0030", X"0000_0000"); -- set BLIT source address 1 + reg_write(X"0000_0034", X"0000_0000"); -- set BLIT source dimension 1 + reg_write(X"0000_0040", X"0000_0000"); -- set BLIT destination address + reg_write(X"0000_0044", X"0000_0000"); -- set BLIT destination dimension -- Enable master reg_write(X"0000_0000", X"0000_0002"); @@ -731,22 +731,22 @@ STIMULUS: process reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x - reg_write(X"0000_0028", to_unsigned(4*32, 32)); + reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address - reg_write(X"0000_0050", X"0000_0000"); + reg_write(X"0000_0040", X"0000_0000"); -- set constant color - reg_write(X"0000_0054", const_color); + reg_write(X"0000_0058", const_color); -- set dst dim-x - reg_write(X"0000_0058", to_unsigned(4*32, 32)); + reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx - reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32)); + reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny - reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32)); + reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); @@ -771,22 +771,22 @@ STIMULUS: process reg_write(X"0000_0020", X"0000_0004"); -- set src dim-x - reg_write(X"0000_0028", to_unsigned(4*32, 32)); + reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address - reg_write(X"0000_0050", X"0000_0000"); + reg_write(X"0000_0040", X"0000_0000"); -- set constant color - reg_write(X"0000_0054", const_color); + reg_write(X"0000_0058", const_color); -- set dst dim-x - reg_write(X"0000_0058", to_unsigned(4*32, 32)); + reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx - reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32)); + reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny - reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32)); + reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); @@ -812,22 +812,22 @@ STIMULUS: process reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x - reg_write(X"0000_0028", to_unsigned(4*32, 32)); + reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address - reg_write(X"0000_0050", X"0000_0004"); + reg_write(X"0000_0040", X"0000_0004"); -- set constant color - reg_write(X"0000_0054", const_color); + reg_write(X"0000_0058", const_color); -- set dst dim-x - reg_write(X"0000_0058", to_unsigned(4*32, 32)); + reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx - reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32)); + reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny - reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32)); + reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); @@ -852,22 +852,22 @@ STIMULUS: process reg_write(X"0000_0020", X"0000_0004"); -- set src dim-x - reg_write(X"0000_0028", to_unsigned(4*32, 32)); + reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address - reg_write(X"0000_0050", X"0000_0004"); + reg_write(X"0000_0040", X"0000_0004"); -- set constant color - reg_write(X"0000_0054", const_color); + reg_write(X"0000_0058", const_color); -- set dst dim-x - reg_write(X"0000_0058", to_unsigned(4*32, 32)); + reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx - reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32)); + reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny - reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32)); + reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); @@ -894,22 +894,22 @@ STIMULUS: process reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x - reg_write(X"0000_0028", to_unsigned(4*32, 32)); + reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address - reg_write(X"0000_0050", X"0000_0000"); + reg_write(X"0000_0040", X"0000_0000"); -- set constant color - reg_write(X"0000_0054", const_color); + reg_write(X"0000_0058", const_color); -- set dst dim-x - reg_write(X"0000_0058", to_unsigned(4*32, 32)); + reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx - reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32)); + reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny - reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32)); + reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); @@ -936,22 +936,22 @@ STIMULUS: process reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x - reg_write(X"0000_0028", to_unsigned(4*32, 32)); + reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address - reg_write(X"0000_0050", X"0000_0004"); + reg_write(X"0000_0040", X"0000_0004"); -- set constant color - reg_write(X"0000_0054", const_color); + reg_write(X"0000_0058", const_color); -- set dst dim-x - reg_write(X"0000_0058", to_unsigned(4*32, 32)); + reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx - reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32)); + reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny - reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32)); + reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd index 7919054..60c1a6c 100644 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/vga_frontend64.vhd @@ -217,6 +217,7 @@ architecture Behavioral of vga_frontend64 is -- BLIT Source register signal blit_src_cnt_x_next : unsigned(32 downto 0); + signal blit_src_cnt_y_next : unsigned(32 downto 0); signal blit_src_cnt_x : unsigned(31 downto 0); signal blit_src_cnt_y : unsigned(31 downto 0); signal blit_src_offset : unsigned(31 downto 0); @@ -233,6 +234,7 @@ architecture Behavioral of vga_frontend64 is -- BLIT Destination register signal blit_dst_cnt_x_next : unsigned(32 downto 0); + signal blit_dst_cnt_y_next : unsigned(32 downto 0); signal blit_dst_cnt_x : unsigned(31 downto 0); signal blit_dst_cnt_y : unsigned(31 downto 0); signal blit_dst_offset : unsigned(31 downto 0); @@ -244,6 +246,7 @@ architecture Behavioral of vga_frontend64 is -- BLIT Source Tracker signal blit_fill_cnt_x_next : unsigned(32 downto 0); + signal blit_fill_cnt_y_next : unsigned(32 downto 0); signal blit_fill_cnt_x : unsigned(31 downto 0); signal blit_fill_cnt_y : unsigned(31 downto 0); signal blit_fill_offset : unsigned(2 downto 0); @@ -903,6 +906,7 @@ blit_dst_suspend_gen: fill_dbg.PARTIAL <= blit_fill_cnt_x_next(32); blit_fill_cnt_x_next <= ('0' & blit_fill_cnt_x - 1) when fill_dbg.FIRST = '1' and fill_dbg.UNALIGNED = '1' else ('0' & blit_fill_cnt_x - 2); + blit_fill_cnt_y_next <= ('0' & blit_fill_cnt_y) - 1; -- BLIT Buffer fill address generator blitfifo_fill_src_0: @@ -921,14 +925,14 @@ blitfifo_fill_src_0: elsif blit_request = '1' and blit_fill_finish = '0' and blit_const_color_en = '0' and blitfifo_write_en = '1' then fill_dbg.FIRST <= '0'; if fill_dbg.LAST = '1' then - if blit_fill_cnt_y < X"0000_0002" then + if blit_fill_cnt_y_next = ('0' & X"0000_0000") or blit_fill_cnt_y_next(32) = '1' then blit_fill_finish <= '1'; else addr_next := (blit_cmd_addr_src_0(31 downto 2) & "00") + blit_fill_offset; blit_fill_addr <= addr_next(2 downto 0); blit_fill_offset <= blit_fill_offset + blit_cmd_dimx_src_0(2 downto 0); blit_fill_cnt_x <= blit_cmd_nx; - blit_fill_cnt_y <= blit_fill_cnt_y - 1; + blit_fill_cnt_y <= blit_fill_cnt_y_next(31 downto 0); fill_dbg.FIRST <= '1'; fill_dbg.UNALIGNED <= addr_next(2); end if; @@ -945,6 +949,7 @@ blitfifo_fill_src_0: blit_src_addr_next <= ADDR_O_blit_src + 8; blit_src_cnt_x_next <= ('0' & blit_src_cnt_x - 1) when src_dbg.FIRST = '1' and src_dbg.UNALIGNED = '1' else ('0' & blit_src_cnt_x - 2); + blit_src_cnt_y_next <= ('0' & blit_src_cnt_y) - 1; -- BLIT Source address generator blit_request_addr_src: @@ -963,16 +968,16 @@ blit_request_addr_src: elsif blit_request = '1' and blit_src_finish = '0' and blit_const_color_en = '0' and (STB_O_blit_src = '1' and busout_fifo_rdy = '1') then src_dbg.FIRST <= '0'; if src_dbg.LAST = '1' then - if blit_src_cnt_y < X"0000_0002" then + if blit_src_cnt_y_next = ('0' & X"0000_0000") or blit_src_cnt_y_next(32) = '1' then blit_src_finish <= '1'; else addr_next := (blit_cmd_addr_src_0(31 downto 2) & "00") + blit_src_offset; ADDR_O_blit_src <= addr_next; blit_src_offset <= blit_src_offset + blit_cmd_dimx_src_0; blit_src_cnt_x <= blit_cmd_nx; - blit_src_cnt_y <= blit_src_cnt_y - 1; + blit_src_cnt_y <= blit_src_cnt_y_next(31 downto 0); src_dbg.FIRST <= '1'; - src_dbg.UNALIGNED <= addr_next(2); + src_dbg.UNALIGNED <= addr_next(2); end if; else ADDR_O_blit_src <= blit_src_addr_next; @@ -988,6 +993,7 @@ blit_request_addr_src: blit_dst_addr_next <= ADDR_O_blit_dst + 8; blit_dst_cnt_x_next <= ('0' & blit_dst_cnt_x - 1) when dst_dbg.FIRST = '1' and dst_dbg.UNALIGNED = '1' else ('0' & blit_dst_cnt_x - 2); + blit_dst_cnt_y_next <= ('0' & blit_dst_cnt_y) - 1; -- BLIT Destination address generator blit_request_addr_dst: @@ -1009,7 +1015,7 @@ blit_request_addr_dst: elsif blit_request = '1' and blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then dst_dbg.FIRST <= '0'; if dst_dbg.LAST = '1' then - if blit_dst_cnt_y < X"0000_0002" then + if blit_dst_cnt_y_next = ('0' & X"0000_0000") or blit_dst_cnt_y_next(32) = '1' then blit_dst_finish <= '1'; blit_finish_strobe(0) <= '1'; else @@ -1017,7 +1023,7 @@ blit_request_addr_dst: ADDR_O_blit_dst <= addr_next; blit_dst_offset <= blit_dst_offset + blit_cmd_dimx_dst; blit_dst_cnt_x <= blit_cmd_nx; - blit_dst_cnt_y <= blit_dst_cnt_y - 1; + blit_dst_cnt_y <= blit_dst_cnt_y_next(31 downto 0); dst_dbg.FIRST <= '1'; dst_dbg.UNALIGNED <= addr_next(2); end if; @@ -1142,8 +1148,8 @@ registers_read: when "01000" => SDAT_O <= blit_reg_addr_src_0; - -- 0x28 - when "01010" => + -- 0x24 + when "01001" => SDAT_O <= blit_reg_dimx_src_0; -- sys_blit_descr_src_1 @@ -1151,32 +1157,34 @@ registers_read: when "01100" => SDAT_O <= blit_reg_addr_src_1; - -- 0x38 - when "01110" => + -- 0x34 + when "01101" => SDAT_O <= blit_reg_dimx_src_1; -- sys_blit_descr_dst - -- 0x50 - when "10100" => + -- 0x40 + when "10000" => SDAT_O <= blit_reg_addr_dst; - when "10101" => - SDAT_O <= blit_reg_const_color; - - -- 0x58 - when "10110" => + -- 0x44 + when "10001" => SDAT_O <= blit_reg_dimx_dst; -- sys_blit_reg_nx - -- 0x60 - when "11000" => + -- 0x50 + when "10100" => SDAT_O <= blit_reg_nx; -- sys_blit_reg_ny - -- 0x64 - when "11001" => + -- 0x54 + when "10101" => SDAT_O <= blit_reg_ny; + -- sys_blit_color + -- 0x58 + when "10110" => + SDAT_O <= blit_reg_const_color; + when others => null; end case; end if; @@ -1272,43 +1280,43 @@ registers_write: when "01000" => blit_reg_addr_src_0 <= SDAT_I(31 downto 0); - -- 0x28 - when "01010" => - blit_reg_dimx_src_0 <= SDAT_I(31 downto 3) & "000"; + -- 0x24 + when "01001" => + blit_reg_dimx_src_0 <= SDAT_I(29 downto 0) & "00"; -- sys_blit_descr_src_1 -- 0x30 when "01100" => blit_reg_addr_src_1 <= SDAT_I(31 downto 0); - -- 0x38 - when "01110" => - blit_reg_dimx_src_1 <= SDAT_I(31 downto 3) & "000"; + -- 0x34 + when "01101" => + blit_reg_dimx_src_1 <= SDAT_I(29 downto 0) & "00"; -- sys_blit_descr_dst - -- 0x50 - when "10100" => + -- 0x40 + when "10000" => blit_reg_addr_dst <= SDAT_I(31 downto 0); - -- sys_blit_reg_const_color - -- 0x54 - when "10101" => - blit_reg_const_color <= SDAT_I(31 downto 0); - - -- 0x58 - when "10110" => - blit_reg_dimx_dst <= SDAT_I(31 downto 3) & "000"; + -- 0x44 + when "10001" => + blit_reg_dimx_dst <= SDAT_I(29 downto 0) & "00"; -- sys_blit_reg_nx - -- 0x60 - when "11000" => + -- 0x50 + when "10100" => blit_reg_nx <= SDAT_I; -- sys_blit_reg_ny - -- 0x64 - when "11001" => + -- 0x54 + when "10101" => blit_reg_ny <= SDAT_I; + -- sys_blit_color + -- 0x58 + when "10110" => + blit_reg_const_color <= SDAT_I; + when others => null; end case;