jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added ac97 Controller

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-21 09:07:16 +00:00
parent c24915c0ba
commit 67d79572d7
58 changed files with 11651 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/ac97_Controller/asm/make
+51
View File
@@ -0,0 +1,51 @@
#!/bin/sh
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: rom-file generation for cpu_core
# Copyright (C) 2007 J. Ahrensfeld
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
# For questions and ideas, please contact the author at jens@jayfield.org
# ---------------------------------------------------------------------
TARGET=$2
DSTDIR=$1
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
$JASM_HOME/jasm.rb $TARGET.jsm
irom_tcl_snippet="$TARGET.irom.tcl.snip"
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
rm -f *.snip
projects/ac97_Controller/asm/test.jsm
+533
View File
@@ -0,0 +1,533 @@
; -------------------------------------------------
; Constants
; -------------------------------------------------
include "../../../lib/jasm/cregs.inc.jsm"
; XIO registers
reg_led: equ 0x00 ; R/W
reg_pcmmode: equ 0x01 ; R/W
reg_freq: equ 0x02 ; R/W
reg_cmd_addr: equ 0x04 ; WO
reg_cmd_data: equ 0x06 ; WO
lcd_port: equ 0x08 ; R/W
reg_mix_dc_adj_left: equ 0x09 ; R/W
reg_mix_dc_adj_right: equ 0x0B ; R/W
reg_pcmin_dc_adj_left: equ 0x0D ; R/W
reg_pcmin_dc_adj_right: equ 0x0F ; R/W
reg_stat_addr: equ 0x04 ; RO
reg_stat_data: equ 0x06 ; RO
reg_btn: equ 0x80 ; RO
reg_dip: equ 0x81 ; RO
reg_pcm_left: equ 0x82 ; RO
reg_pcm_right: equ 0x84 ; RO
reg_mix_x_left: equ 0x86 ; RO
reg_mix_x_right: equ 0x88 ; RO
reg_mix_y_left: equ 0x8A ; RO
reg_mix_y_right: equ 0x8C ; RO
reg_stat_hw: equ 0xA0 ; RO
reg_beef: equ 0x8E
; reg_stat_hw
; Bits
omsk_ac_rdy: equ 0x01
omsk_cmd_rdy: equ 0x02
omsk_stat_rdy: equ 0x04
omsk_fir_rdy: equ 0x08
; Flag masks
omsk_led0: equ 0x01
omsk_led1: equ 0x02
omsk_led2: equ 0x04
omsk_led3: equ 0x08
amsk_led0: equ 0xFE
amsk_led1: equ 0xFD
amsk_led2: equ 0xFB
amsk_led3: equ 0xF7
omsk_btn_W: equ 0x01
omsk_btn_N: equ 0x02
omsk_btn_E: equ 0x04
omsk_btn_S: equ 0x08
omsk_btn_C: equ 0x10
DC_CORR_PCM: equ 0xFF40
DC_CORR_MIX: equ 0x005C
NCO_FREQ: equ 0x4000
BAR_UPD_INTERVAL: equ 0x0080
; -------------------------------------------------
; On-Chip memory
; -------------------------------------------------
cmem 0
btn_state: db 1
dip_state: db 1
stat_addr: db 2
stat_data: db 2
bar_value: db 2
bar_data: db 2
lcd_disp: db 4
bar_upd_count: db 2
count: db 2
xmem
msg_txt: dc "AC'97 Test V1.2", 0
ac97_cfg_addr: dc 0x00, 0x2A ; W: Extended Audio CTRL/STATUS
dc 0x00, 0x1A ; W: Record select
dc 0x00, 0x1C ; W: Record gain
dc 0x00, 0x2C ; W: PCM DAC rate
dc 0x00, 0x32 ; W: PCM ADC rate
dc 0x00, 0x20 ; W: General purpose
dc 0x00, 0x02 ; W: Master volume
dc 0x00, 0x04 ; W: Headphone volume
dc 0x00, 0x18 ; W: PCM volume
ac97_cfg_data: dc 0x01, 0x00 ; W: VRA=1
dc 0x04, 0x04 ; W: Record source = LINE_IN
dc 0x00, 0x00 ; W: Record gain = 0dB
dc 0x80, 0xBB ; W: DAC rate 48000Hz
dc 0x80, 0xBB ; W: ADC rate 48000Hz
dc 0x00, 0x80 ; W: POP=1
dc 0x00, 0x00 ; W: Master volume = 0dB
dc 0x00, 0x00 ; W: Headphone volume = 0dB, muted
dc 0x0A, 0x0A ; W: PCM volume = -3dB
; -------------------------------------------------
; Program
; -------------------------------------------------
code
org 0x000
reset: jmp init
org 0x001
jmp frame_isr
; -------------------------------------------------
; Main
; -------------------------------------------------
init: mov R0, 0x00
mov R1, 0x00
mov R2, 0x00
mov R3, 0x00
xout (reg_led), R0
movc (btn_state), R0
movc (count+0), R0
movc (count+1), R0
movc (bar_data+0), R0
movc (bar_data+1), R0
mov R0, BAR_UPD_INTERVAL,'low
mov R1, BAR_UPD_INTERVAL,'high
movc (bar_upd_count+0), R0
movc (bar_upd_count+1), R1
call LCD_init
call LCD_INIT_CGRAM
; Print Hello world
mov R0, LCD_CMD_CLEAR
call LCD_writecmd
mov R1, msg_txt
call LCD_putsx
wait_ac_rdy: xin R0, (reg_stat_hw)
and R0, omsk_ac_rdy
jz wait_ac_rdy
wait_fir_rdy: xin R0, (reg_stat_hw)
and R0, omsk_fir_rdy
jz wait_fir_rdy
call delay1s
; Send AC97 Status register read-request (CODEC_ID)
mov R0, 0x00
mov R1, 0x80
mov R2, 0x00
mov R3, 0x00
call AC_status_io
movc (stat_addr+0), R0
movc (stat_addr+1), R1
movc (stat_data+0), R2
movc (stat_data+1), R3
; Initialize AC97
; check status
ac97_rdy_lp: mov R0, 0x00
mov R1, 0xA6
mov R2, 0x00
mov R3, 0x00
call AC_status_io
and R2, 0x0F
cmp R2, 0x0F
jne ac97_rdy_lp
mov R15, 9
mov R7, ac97_cfg_addr
mov R8, ac97_cfg_data
ac97_init_lp: movx R0, (R7)
inc R7
movx R1, (R7)
inc R7
movx R2, (R8)
inc R8
movx R3, (R8)
inc R8
call AC_status_io
dec R15
jnz ac97_init_lp
; Print status address
label: mov R0, LCD_CMD_CLEAR
call LCD_writecmd
mov R0, 65
call LCD_writechar
mov R0, 58
call LCD_writechar
movc R0, (stat_addr+1)
call PutHexByte
movc R0, (stat_addr+0)
call PutHexByte
; Print status data
mov R0, 32
call LCD_writechar
mov R0, 68
call LCD_writechar
mov R0, 58
call LCD_writechar
movc R0, (stat_data+1)
call PutHexByte
movc R0, (stat_data+0)
call PutHexByte
; Set PCM mode
mov R0, 0x00
xout (reg_pcmmode), R0
; Set NCO frequency
mov R0, NCO_FREQ'high
xout (reg_freq+1), R0
mov R0, NCO_FREQ'low
xout (reg_freq+0), R0
; PCM-IN: Set DC correction LEFT
mov R0, DC_CORR_PCM'high
xout (reg_pcmin_dc_adj_left+1), R0
mov R0, DC_CORR_PCM'low
xout (reg_pcmin_dc_adj_left+0), R0
; PCM-IN: Set DC correction RIGHT
mov R0, DC_CORR_PCM'high
xout (reg_pcmin_dc_adj_right+1), R0
mov R0, DC_CORR_PCM'low
xout (reg_pcmin_dc_adj_right+0), R0
; Mixer: Set DC correction LEFT
mov R0, DC_CORR_MIX'high
xout (reg_mix_dc_adj_left+1), R0
mov R0, DC_CORR_MIX'low
xout (reg_mix_dc_adj_left+0), R0
; Mixer: Set DC correction RIGHT
mov R0, DC_CORR_MIX'high
xout (reg_mix_dc_adj_right+1), R0
mov R0, DC_CORR_MIX'low
xout (reg_mix_dc_adj_right+0), R0
; Switch on LED
xin R0, (reg_led)
or R0, omsk_led0
xout (reg_led), R0
; Enable Interrupt
mov R0, 0x07
cout (cpu_int_ctrl), R0
; Sample switches and buttons
main: xin R0, (reg_dip)
movc (dip_state), R0
xin R0, (reg_btn)
movc (btn_state), R0
movc R0, (dip_state)
xout (reg_pcmmode), R0
xin R0, (reg_led)
and R0, omsk_led3
jnz main
mov R0, LCD_CMD_Z2
call LCD_writecmd
movc R0, (btn_state)
and R0, omsk_btn_C
jnz disp_mix
xin R0, (reg_pcm_left+0)
movc (lcd_disp+0), R0
xin R0, (reg_pcm_left+1)
movc (lcd_disp+1), R0
xin R0, (reg_pcm_right+0)
movc (lcd_disp+2), R0
xin R0, (reg_pcm_right+1)
movc (lcd_disp+3), R0
jmp print
disp_mix: xin R0, (reg_mix_x_left+0)
movc (lcd_disp+0), R0
xin R0, (reg_mix_x_left+1)
movc (lcd_disp+1), R0
xin R0, (reg_mix_x_right+0)
movc (lcd_disp+2), R0
xin R0, (reg_mix_x_right+1)
movc (lcd_disp+3), R0
print: call bar_div
mov R0, 76
call LCD_writechar
mov R0, 58
call LCD_writechar
movc R0, (lcd_disp+1)
call PutHexByte
movc R0, (lcd_disp+0)
call PutHexByte
mov R0, 32
call LCD_writechar
mov R0, 82
call LCD_writechar
mov R0, 58
call LCD_writechar
movc R0, (lcd_disp+3)
call PutHexByte
movc R0, (lcd_disp+2)
call PutHexByte
chk_wm: movc R0, (btn_state)
and R0, omsk_btn_W
jz chk_em
; Decrease NCO frequency
xin R0, (reg_freq+0)
xin R1, (reg_freq+1)
sub R0, 0x64
jnc upd_regs
dec R1
jmp upd_regs
chk_em: movc R0, (btn_state)
and R0, omsk_btn_E
jz ex_chk
; Increase NCO frequency
xin R0, (reg_freq+0)
xin R1, (reg_freq+1)
add R0, 0x64
jnc upd_regs
inc R1
jmp upd_regs
upd_regs: xout (reg_freq+1), R1
xout (reg_freq+0), R0
w4led: xin R0, (reg_led)
and R0, omsk_led3
jz w4led
ex_chk: jmp main
; -------------------------------------------------
frame_isr: push R0
push R1
movc R0, (count+0)
movc R1, (count+1)
inc R0
cmp R0, 0x30
jnz ex_isr
mov R0, 0
push R0
xin R0, (reg_btn)
movc (btn_state), R0
pop R0
inc R1
cmp R1, 0x64
jnz ex_isr
call subr
mov R1, 0
ex_isr: movc (count+0), R0
movc (count+1), R1
pop R1
pop R0
reti
; -------------------------------------------------
subr: xin R0, (reg_led)
mov R1, R0
and R1, omsk_led3
jnz switch_off
or R0, omsk_led3
jmp switch
switch_off: and R0, amsk_led3
switch: xout (reg_led), R0
ret
; -------------------------------------------------
; AC Read/Write register
; R0 : IN/OUT AC register address 7..0. Written, if cmd was READ (i.e. address[15] = 1)
; R1 : IN/OUT AC register address 15..8. Written, if cmd was READ (i.e. address[15] = 1)
; R2 : IN/OUT AC register data 7..0. Written, if cmd was READ (i.e. address[15] = 1)
; R3 : IN/OUT AC register data 15..8. Written, if cmd was READ (i.e. address[15] = 1)
AC_status_io: call wait_cmd_rdy
xout (reg_cmd_addr+1), R1
xout (reg_cmd_addr+0), R0
xout (reg_cmd_data+1), R3
xout (reg_cmd_data+0), R2
; Check if command was read
and R1, 0x80
jnz wait_read
ret
; Wait for READ command being processed
wait_read: call wait_stat_rdy
; Read AC97 Status register address
xin R1, (reg_stat_addr+1)
xin R0, (reg_stat_addr+0)
; Read AC97 Status register data
xin R3, (reg_stat_data+1)
xin R2, (reg_stat_data+0)
ret
; -------------------------------------------------
wait_cmd_rdy: push R0
wcr_loop: xin R0, (reg_stat_hw)
and R0, omsk_cmd_rdy
jz wcr_loop
pop R0
ret
; -------------------------------------------------
wait_stat_rdy: push R0
wsr_loop: xin R0, (reg_stat_hw)
and R0, omsk_stat_rdy
jz wsr_loop
pop R0
ret
; -------------------------------------------------
; PutHexByte
; R0 : Byte value
PutHexByte: call bin2hex
call LCD_writechar
mov R0, R1
call LCD_writechar
ret
; -------------------------------------------------
; Init LCD CG-RAM
LCD_INIT_CGRAM:
mov R0, 0x40
call LCD_writecmd
mov R1, 0xE0
mov R15, 6
write_char: mov R14, 7
write_cols: mov R0, R1
call LCD_writedata
dec R14
jnz write_cols
mov R0, 0
call LCD_writedata
mov R0, 1
shr R0
rorc R1
dec R15
jnz write_char
ret
; -------------------------------------------------
bar_div:
push R0
push R1
push R15
movc R0, (bar_upd_count+0)
movc R1, (bar_upd_count+1)
dec R0
subc R1, 0
movc (bar_upd_count+0), R0
movc (bar_upd_count+1), R1
tst R1
jz chk_lsb
jmp ex_div
chk_lsb: tst R0
jz reload
jmp ex_div
reload: mov R0, BAR_UPD_INTERVAL,'low
mov R1, BAR_UPD_INTERVAL,'high
movc (bar_upd_count+0), R0
movc (bar_upd_count+1), R1
mov R15, 11
mov R0, 0
movc R1, (lcd_disp+1)
cmp R1, 0x80
jge skip_l
go_l: movc R1, (lcd_disp+1)
movc R0, (lcd_disp+0)
div_lp_l: shr R1
rorc R0
dec R15
jnz div_lp_l
skip_l: movc (bar_value+0), R0
mov R15, 11
mov R0, 0
movc R1, (lcd_disp+3)
cmp R1, 0x80
jge skip_r
go_r: movc R0, (lcd_disp+2)
movc R1, (lcd_disp+3)
div_lp_r: shr R1
rorc R0
dec R15
jnz div_lp_r
skip_r: movc (bar_value+1), R0
movc R0, (bar_value+0)
movc R1, (bar_data+0)
tst R1
jz bot_l
dec R1
bot_l: cmp R0, R1
jlt no_upd_l
mov R1, R0
no_upd_l: movc (bar_data+0), R1
movc R0, (bar_value+1)
movc R1, (bar_data+1)
tst R1
jz bot_r
dec R1
bot_r: cmp R0, R1
jlt no_upd_r
mov R1, R0
no_upd_r: movc (bar_data+1), R1
ex_div: pop R15
pop R1
pop R0
ret
include "../../../lib/jasm/delays.inc.jsm"
include "../../../lib/jasm/lcd.inc.jsm"
include "../../../lib/jasm/utils.inc.jsm"
projects/ac97_Controller/asm/test.tcl
+1638
View File
File diff suppressed because it is too large Load Diff
projects/ac97_Controller/asm/test_irom.tcl
+1191
View File
File diff suppressed because it is too large Load Diff
projects/ac97_Controller/asm/test_xrom.tcl
+66
View File
@@ -0,0 +1,66 @@
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: The ROM file for upload to target over JTAG
# Copyright (C) 2007 J. Ahrensfeld
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
# For questions and ideas, please contact the author at jens@jayfield.org
# ---------------------------------------------------------------------
# ---------------------------------------------------------------------
# For Chipscope 9.1
# ---------------------------------------------------------------------
# Source JTAG/TCL frame work
cd $env(CHIPSCOPE)\\bin\\nt
source csejtag.tcl
namespace import ::chipscope::*
# Platform USB Cable
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" \
"frequency=1500000"]
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
# Create session
set handle [::chipscope::csejtag_session create 0]
# Open JTAG and lock
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
set lock_result [::chipscope::csejtag_target lock $handle 1000]
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
# Get Device ID
set devtype "Virtex-4SX"
set devid 2
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
# ---------------------------------------------------------------
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
# User 2
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 $irlength "3C3"]
# Write Program
# JASM_ROM_INSERT_HERE
# Assembled from test.jsm
::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
::chipscope::csejtag_session destroy $handle
exit
projects/ac97_Controller/ise91/fir_bandpass/project/syn_fir_bandpass.lso
+1
View File
@@ -0,0 +1 @@
work
projects/ac97_Controller/ise91/fir_bandpass/project/syn_fir_bandpass.prj
+7
View File
@@ -0,0 +1,7 @@
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
vhdl work "../../../../lib/filter/src/filter_pkg.vhd"
vhdl work "../../../../lib/filter/src/fir_stage_pkg.vhd"
vhdl work "../../../../lib/filter/src/fir_iterative_pkg.vhd"
vhdl work "../../../../lib/filter/src/fir_stage.vhd"
vhdl work "../../../../lib/filter/src/fir_iterative.vhd"
vhdl work "../../src/syn_fir_bandpass.vhd"
projects/ac97_Controller/ise91/fir_bandpass/project/syn_fir_bandpass.xst
+59
View File
@@ -0,0 +1,59 @@
set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn syn_fir_bandpass.prj
-ifmt mixed
-ofn syn_fir_bandpass
-ofmt NGC
-p xc4vsx35-10-ff668
-top syn_fir_bandpass
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso syn_fir_bandpass.lso
-keep_hierarchy YES
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/ac97_Controller/ise91/fir_lowpass/project/syn_fir_lowpass.lso
+2
View File
@@ -0,0 +1,2 @@
ieee_proposed
work
projects/ac97_Controller/ise91/fir_lowpass/project/syn_fir_lowpass.prj
+11
View File
@@ -0,0 +1,11 @@
vhdl ieee_proposed "../../../../lib/fixed/xilinx/math_utility_pkg.vhdl"
vhdl ieee_proposed "../../../../lib/fixed/xilinx/fixed_pkg_c.vhdl"
vhdl work "../../../../lib/fixed/fixed_util_pkg.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/filter/src/filter_pkg.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/filter/src/fir_pkg.vhd"
vhdl work "../../../../lib/filter/src/fir_stage_sys.vhd"
vhdl work "../../../../lib/filter/src/delay_line.vhd"
vhdl work "../../../../lib/filter/src/fir_semi_parallel.vhd"
vhdl work "../../src/syn_fir_lowpass_sp.vhd"
projects/ac97_Controller/ise91/fir_lowpass/project/syn_fir_lowpass.xst
+60
View File
@@ -0,0 +1,60 @@
set -tmpdir "W:/vhdl/projects/ac97_Controller/ise91/fir_lowpass/xst/projnav.tmp"
set -xsthdpdir "W:/vhdl/projects/ac97_Controller/ise91/fir_lowpass/xst"
run
-ifn syn_fir_lowpass.prj
-ifmt mixed
-ofn syn_fir_lowpass
-ofmt NGC
-p xc4vsx35-10-ff668
-top syn_fir_lowpass
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso syn_fir_lowpass.lso
-keep_hierarchy YES
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/ac97_Controller/ise91/nco_netlist/project/syn_nco.lso
+1
View File
@@ -0,0 +1 @@
work
projects/ac97_Controller/ise91/nco_netlist/project/syn_nco.prj
+6
View File
@@ -0,0 +1,6 @@
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
vhdl work "../../../../lib/radio/nco/src/nco_pkg.vhd"
vhdl work "../../../../lib/radio/nco/src/waverom_dual.vhd"
vhdl work "../../../../lib/radio/nco/src/wavelut.vhd"
vhdl work "../../../../lib/radio/nco/src/nco.vhd"
vhdl work "../../src/syn_nco.vhd"
projects/ac97_Controller/ise91/nco_netlist/project/syn_nco.xst
+59
View File
@@ -0,0 +1,59 @@
set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn syn_nco.prj
-ifmt mixed
-ofn syn_nco
-ofmt NGC
-p xc4vsx35-10-ff668
-top syn_nco
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso syn_nco.lso
-keep_hierarchy YES
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/ac97_Controller/ise91/systest/project/ac97.ucf
+97
View File
@@ -0,0 +1,97 @@
CONFIG STEPPING="ES";
# Bus clock nets
NET "sys_clk_in" TNM_NET = "sys_clk";
NET "ac97_bit_clk" TNM_NET = "ac97_clk";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
TIMESPEC "TSBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET sys_rst_n_in LOC = D6;
NET sys_rst_n_in PULLUP;
NET sys_rst_n_in TIG;
////////////////////////////////////////////////////////////////////////////
// AC97 Sound Controller
////////////////////////////////////////////////////////////////////////////
NET ac97_bit_clk LOC = AE10;
NET ac97_bit_clk IOSTANDARD = LVCMOS33;
NET ac97_bit_clk PERIOD = 80;
NET ac97_sdata_in LOC = AD16;
NET ac97_sdata_in IOSTANDARD = LVCMOS33;
NET ac97_reset_n LOC = AD10;
NET ac97_reset_n IOSTANDARD = LVCMOS33;
NET ac97_reset_n TIG;
NET ac97_reset_n SLEW = SLOW;
NET ac97_sdata_out LOC = C8;
NET ac97_sdata_out SLEW = FAST;
NET ac97_sync LOC = D9;
NET ac97_sync SLEW = FAST;
////////////////////////////////////////////////////////////////////////////
// RS-232
////////////////////////////////////////////////////////////////////////////
NET sys_rx LOC = W2;
NET sys_rx IOSTANDARD = LVCMOS33;
NET sys_rx TIG;
NET "sys_tx" LOC = "W1";
NET sys_tx IOSTANDARD = LVCMOS33;
NET "sys_tx" TIG;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
NET "sys_led<*>" TIG;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;
////////////////////////////////////////////////////////////////////////////
// LCD
////////////////////////////////////////////////////////////////////////////
NET sys_lcd_e LOC = AE13; # LCD_E
NET sys_lcd_e IOSTANDARD = LVCMOS33;
NET sys_lcd_e TIG;
NET sys_lcd_rs LOC = AC17; # LCD_RS
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
NET sys_lcd_rs TIG;
NET sys_lcd_rw LOC = AB17; # LCD_RW
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
NET sys_lcd_rw TIG;
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
NET sys_lcd_d<*> TIG;
NET sys_lcd_d<*> PULLDOWN;
projects/ac97_Controller/ise91/systest/project/ac97_test.lso
+1
View File
@@ -0,0 +1 @@
work
projects/ac97_Controller/ise91/systest/project/ac97_test.prj
+13
View File
@@ -0,0 +1,13 @@
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
vhdl work "../../../../lib/radio/mix/src/mix_pkg.vhd"
vhdl work "../../../../lib/misc/singleshot.vhd"
vhdl work "../../src/test_irom_ld.vhdl"
vhdl work "../../src/ac_out.vhd"
vhdl work "../../src/ac_in.vhd"
vhdl work "../../src/test_xrom_ld.vhdl"
vhdl work "../../src/cpu_embedded.vhd"
vhdl work "../../src/ac_io.vhd"
vhdl work "../../../../lib/radio/mix/src/mix_cpx.vhd"
vhdl work "../../../../lib/misc/lcd_port.vhd"
vhdl work "../../src/ac97_test.vhd"
projects/ac97_Controller/ise91/systest/project/ac97_test.ucf
View File
projects/ac97_Controller/ise91/systest/project/ac97_test.ut
+33
View File
@@ -0,0 +1,33 @@
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:Auto
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/ac97_Controller/ise91/systest/project/ac97_test.xst
+59
View File
@@ -0,0 +1,59 @@
set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn ac97_test.prj
-ifmt mixed
-ofn ac97_test
-ofmt NGC
-p xc4vsx35-10-ff668
-top ac97_test
-opt_mode Speed
-opt_level 2
-power NO
-iuc NO
-lso ac97_test.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob true
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/ac97_Controller/make.sh
+17
View File
@@ -0,0 +1,17 @@
#!/bin/sh
# ------------------------------------------------
unit_to_run="tb_eval_fixed_ja"
# ------------------------------------------------
std_opt="--workdir=work --std=93c --ieee=standard"
srcdir=./src
# ------------------------------------------------
ghdl --remove $std_opt
ghdl -i $std_opt $srcdir/*.vhd
ghdl -a $std_opt $srcdir/*.vhd
ghdl -m $std_opt $unit_to_run
ghdl -r $unit_to_run --vcd=$unit_to_run.vcd --assert-level=error
# ------------------------------------------------
projects/ac97_Controller/make_pcm.sh
+17
View File
@@ -0,0 +1,17 @@
#!/bin/sh
# ------------------------------------------------
unit_to_run="tb_pcm_vhd"
# ------------------------------------------------
std_opt="--workdir=work --std=93c --ieee=synopsys"
srcdir=./src
# ------------------------------------------------
ghdl --remove $std_opt
ghdl -i $std_opt $srcdir/*.vhd
ghdl -a $std_opt $srcdir/*.vhd
ghdl -m $std_opt $unit_to_run
ghdl -r $unit_to_run --vcd=$unit_to_run.vcd --assert-level=error
# ------------------------------------------------
projects/ac97_Controller/quartus/fir_lowpass/syn_fir_lowpass.out.sdc
+107
View File
@@ -0,0 +1,107 @@
## Generated SDC file "syn_fir_lowpass.out.sdc"
## Copyright (C) 1991-2008 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
## DATE "Wed Dec 31 12:25:32 2008"
##
## DEVICE "EP3C25F324C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clkin} -period 7.500 [get_ports {clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_max_delay -from [all_inputs] -to [get_clocks clkin] 2.0
#**************************************************************
# Set Output Delay
#**************************************************************
set_max_delay -from [all_outputs] -to [get_clocks clkin] 1.5
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -through [get_pins {rst}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
projects/ac97_Controller/quartus/fir_lowpass/syn_fir_lowpass.out.sdc.bak
+107
View File
@@ -0,0 +1,107 @@
## Generated SDC file "syn_fir_lowpass.out.sdc"
## Copyright (C) 1991-2008 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
## DATE "Wed Dec 31 12:25:32 2008"
##
## DEVICE "EP3C25F324C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk166} -period 7.500 [get_ports {clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_max_delay -from [all_inputs] -to [get_clocks clk166] 2.0
#**************************************************************
# Set Output Delay
#**************************************************************
set_max_delay -from [all_outputs] -to [get_clocks clk166] 1.5
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -through [get_pins {rst}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
projects/ac97_Controller/quartus/fir_lowpass/syn_fir_lowpass.qpf
+23
View File
@@ -0,0 +1,23 @@
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "8.1"
DATE = "11:53:04 December 31, 2008"
# Revisions
PROJECT_REVISION = "syn_fir_lowpass"
projects/ac97_Controller/quartus/fir_lowpass/syn_fir_lowpass.qsf
+62
View File
@@ -0,0 +1,62 @@
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# syn_fir_lowpass_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25F324C6
set_global_assignment -name TOP_LEVEL_ENTITY syn_fir_lowpass
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:53:04 DECEMBER 31, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name DSP_BLOCK_BALANCING AUTO
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name SDC_FILE syn_fir_lowpass.out.sdc
set_global_assignment -name VHDL_FILE ../../../../lib/misc/dpram_1w1r.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_semi_parallel.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/delay_line.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/syn_fir_lowpass_sp.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_stage_sys.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/fixed_util_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/altera/math_utility_pkg.vhdl
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/altera/fixed_pkg_c.vhdl
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/filter_pkg.vhd
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
projects/ac97_Controller/quartus/fir_lowpass/syn_fir_lowpass.qws
+18
View File
@@ -0,0 +1,18 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=../../src/syn_fir_lowpass_sp.vhd
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
projects/ac97_Controller/quartus/fir_lowpass/syn_fir_lowpass.sdc
+56
View File
@@ -0,0 +1,56 @@
###########################################################################
#
# Generated by : Version 8.1 Build 163 10/28/2008 SJ Web Edition
#
# Project : syn_fir_lowpass
# Revision : syn_fir_lowpass
#
# Date : Wed Dec 31 12:24:38 Westeuropäische Normalzeit 2008
#
###########################################################################
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
# In SDC, create_generated_clock auto-generates clock latency
#
# ------------------------------------------
#
# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
#
# ------------------------------------------
# ** Clock Latency
# -------------
# ** Clock Uncertainty
# -----------------
# ** Multicycles
# -----------
# ** Cuts
# ----
# ** Input/Output Delays
# -------------------
# ** Tpd requirements
# ----------------
# ** Setup/Hold Relationships
# ------------------------
# ** Tsu/Th requirements
# -------------------
# ** Tco/MinTco requirements
# -----------------------
# ---------------------------------------------
projects/ac97_Controller/sim/tb_ac97_test.fdo
+48
View File
@@ -0,0 +1,48 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jun 16 12:40:53 Westeuropäische Sommerzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../../../lib/radio/nco/src/nco_pkg.vhd"
vcom -explicit -93 "../../../lib/radio/nco/src/nco.vhd"
vcom -explicit -93 "../../../lib/radio/nco/src/wavelut.vhd"
vcom -explicit -93 "../../../lib/radio/nco/src/waverom_dual.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/stack_ctrl.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/reg_dual.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/chipram.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/chipreg.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/pc.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/dpath_ctrl.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/int_ctrl.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/alu.vhd"
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu.vhd"
vcom -explicit -93 "../src/test_irom.vhdl"
vcom -explicit -93 "../src/test_xrom.vhdl"
vcom -explicit -93 "../src/cpu_embedded.vhd"
vcom -explicit -93 "../../../lib/filter/src/filter_pkg.vhd"
vcom -explicit -93 "../../../lib/filter/src/fir_stage_pkg.vhd"
vcom -explicit -93 "../../../lib/filter/src/fir_stage.vhd"
vcom -explicit -93 "../../../lib/filter/src/fir_iterative_pkg.vhd"
vcom -explicit -93 "../../../lib/filter/src/fir_iterative.vhd"
vcom -explicit -93 "../src/syn_fir_bandpass.vhd"
vcom -explicit -93 "../src/syn_fir_lowpass.vhd"
vcom -explicit -93 "../../../lib/radio/mix/src/mix_pkg.vhd"
vcom -explicit -93 "../../../lib/radio/mix/src/mix_cpx.vhd"
vcom -explicit -93 "../src/syn_nco.vhd"
vcom -explicit -93 "../src/ac_out.vhd"
vcom -explicit -93 "../src/ac_in.vhd"
vcom -explicit -93 "../src/ac_io.vhd"
vcom -explicit -93 "../src/ac97_test.vhd"
vcom -explicit -93 "../src/tb_ac97_test.vhd"
vsim -t 1ps -lib work tb_ac97_test
view wave
do {tb_ac97_test.wdo}
view structure
view signals
run 50us
projects/ac97_Controller/sim/tb_ac97_test.ndo
+14
View File
@@ -0,0 +1,14 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../eval_ac/netgen/translate/ac97_test_translate.vhd"
vcom -explicit -93 "../src/tb_ac97_test.vhd"
vsim -t 1ps -lib work tb_ac97_test
do {tb_ac97_test.wdo}
view wave
view structure
view signals
run 200us
## End
projects/ac97_Controller/sim/tb_ac97_test.sdo
+14
View File
@@ -0,0 +1,14 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../eval_ac/netgen/synthesis/ac97_test_synthesis.vhd"
vcom -explicit -93 "../src/tb_ac97_test.vhd"
vsim -t 1ps -lib work tb_ac97_test
do {tb_ac97_test.wdo}
view wave
view structure
view signals
run 200us
## End
projects/ac97_Controller/sim/tb_ac97_test.wdo
+40
View File
@@ -0,0 +1,40 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac97_test/uut/inst_mix_cpx/srst
add wave -noupdate -format Logic /tb_ac97_test/uut/inst_mix_cpx/clk
add wave -noupdate -format Logic /tb_ac97_test/uut/inst_mix_cpx/in_valid
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/x_re_in
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/x_im_in
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/y_re_in
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/y_im_in
add wave -noupdate -format Logic /tb_ac97_test/uut/inst_mix_cpx/out_valid
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/z_re_out
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/z_im_out
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/x_re
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/x_im
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/y_re
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/y_im
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/p_re_left
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/p_re_right
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/p_im_left
add wave -noupdate -format Literal /tb_ac97_test/uut/inst_mix_cpx/p_im_right
add wave -noupdate -format Logic /tb_ac97_test/uut/inst_mix_cpx/valid
add wave -noupdate -format Logic /tb_ac97_test/uut/inst_mix_cpx/p_valid
add wave -noupdate -format Literal /tb_ac97_test/uut/cpu_pcm_in_dc_left
add wave -noupdate -format Literal /tb_ac97_test/uut/cpu_pcm_in_dc_right
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {1852395000 ps} 0} {{Cursor 2} {63210702 ps} 0} {{Cursor 4} {4999959266 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {525 us}
projects/ac97_Controller/sim/tb_ac_in.fdo
+14
View File
@@ -0,0 +1,14 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd"
vcom -explicit -93 "../src/ac_out.vhd"
vcom -explicit -93 "../src/ac_in.vhd"
vcom -explicit -93 "../src/tb_ac_in.vhd"
vsim -t 1ps -lib work tb_ac_in
do {tb_ac_in.wdo}
view wave
view structure
view signals
run 700us
projects/ac97_Controller/sim/tb_ac_in.wdo
+43
View File
@@ -0,0 +1,43 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac_in/uut/rst
add wave -noupdate -format Logic /tb_ac_in/uut/clk
add wave -noupdate -format Logic /tb_ac_in/uut/sync_frame
add wave -noupdate -format Logic /tb_ac_in/uut/sync_status
add wave -noupdate -divider {AC97 lines}
add wave -noupdate -format Logic /tb_ac_in/uut/ac_reset
add wave -noupdate -format Logic /tb_ac_in/uut/ac_bit_clk
add wave -noupdate -format Logic /tb_ac_in/uut/ac_sdata_in
add wave -noupdate -format Logic /tb_ac_in/uut/ac_ssync
add wave -noupdate -divider Debug
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_data
add wave -noupdate -format Literal /tb_ac_in/uut/pcm_out_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/pcm_out_data
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ac_in/uut/data_array
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/tag
add wave -noupdate -format Literal /tb_ac_in/uut/sac
add wave -noupdate -format Literal /tb_ac_in/uut/bitcnt
add wave -noupdate -format Literal /tb_ac_in/uut/slotcnt
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/rx_reg
add wave -noupdate -format Logic /tb_ac_in/uut/stat_read
add wave -noupdate -format Logic /tb_ac_in/uut/host_update
add wave -noupdate -format Logic /tb_ac_in/uut/slot_end
add wave -noupdate -format Logic /tb_ac_in/uut/sync_end
add wave -noupdate -format Logic /tb_ac_in/uut/last_slot
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {53431686 ps} 0} {{Cursor 2} {44308511 ps} 0} {{Cursor 4} {677821715 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {52190046 ps} {56168939 ps}
projects/ac97_Controller/sim/tb_ac_io.fdo
+15
View File
@@ -0,0 +1,15 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../src/ac_out.vhd"
vcom -explicit -93 "../src/ac_in.vhd"
vcom -explicit -93 "../src/ac_io.vhd"
vcom -explicit -93 "../src/tb_ac_io.vhd"
vsim -t 1ps -lib work tb_ac_io
do {tb_ac_io.wdo}
view wave
view structure
view signals
run 700us
projects/ac97_Controller/sim/tb_ac_io.wdo
+51
View File
@@ -0,0 +1,51 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac_io/uut/rst
add wave -noupdate -format Logic /tb_ac_io/uut/clk
add wave -noupdate -format Logic /tb_ac_io/uut/ready
add wave -noupdate -format Literal /tb_ac_io/uut/slot_valid
add wave -noupdate -format Logic /tb_ac_io/uut/sync_strobe
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_data
add wave -noupdate -format Literal /tb_ac_io/uut/rx_pcm_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/rx_pcm_data
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_data
add wave -noupdate -format Logic /tb_ac_io/uut/cmd_we
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_data
add wave -noupdate -format Logic /tb_ac_io/uut/tx_pcm_we
add wave -noupdate -divider {AC97 lines}
add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_in
add wave -noupdate -format Logic /tb_ac_io/uut/ac_bit_clk
add wave -noupdate -format Logic /tb_ac_io/uut/ac_reset_n
add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_out
add wave -noupdate -format Logic /tb_ac_io/uut/ac_ssync
add wave -noupdate -divider Debug
add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_in/stat_read
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/rx_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_out/tx_reg
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/bitcnt
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/sac
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/tag
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/data_array
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/bitcnt
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slotcnt
add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_out/ssync
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slot_valid
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {0 ps} 0} {{Cursor 2} {292930000 ps} 0} {{Cursor 4} {4999959266 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {735 us}
projects/ac97_Controller/sim/tb_ac_out.fdo
+13
View File
@@ -0,0 +1,13 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd"
vcom -explicit -93 "../src/ac_out.vhd"
vcom -explicit -93 "../src/tb_ac_out.vhd"
vsim -t 1ps -lib work tb_ac_out
do {tb_ac_out.wdo}
view wave
view structure
view signals
run 600us
projects/ac97_Controller/sim/tb_ac_out.wdo
+41
View File
@@ -0,0 +1,41 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac_out/rst
add wave -noupdate -format Logic /tb_ac_out/clk
add wave -noupdate -format Logic /tb_ac_out/ce
add wave -noupdate -divider {Host hand shake}
add wave -noupdate -format Logic /tb_ac_out/sync_tx
add wave -noupdate -divider {Command I/F}
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_data
add wave -noupdate -format Logic /tb_ac_out/uut/cmd_we
add wave -noupdate -divider {PCM I/F}
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_data
add wave -noupdate -format Logic /tb_ac_out/pcm_in_we
add wave -noupdate -divider {AC97 I/F}
add wave -noupdate -format Logic /tb_ac_out/ac_bit_clk
add wave -noupdate -format Logic /tb_ac_out/ac_reset
add wave -noupdate -format Logic /tb_ac_out/ac_sdata_out
add wave -noupdate -format Logic /tb_ac_out/ac_ssync
add wave -noupdate -divider Debug
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/uut/tx_reg
add wave -noupdate -format Literal /tb_ac_out/uut/sac
add wave -noupdate -format Literal /tb_ac_out/uut/bitcnt
add wave -noupdate -format Literal /tb_ac_out/uut/slotcnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {544839100 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {532851785 ps} {556826415 ps}
projects/ac97_Controller/src/ac97_test.old.vhd
+1067
View File
File diff suppressed because it is too large Load Diff
projects/ac97_Controller/src/ac97_test.vhd
+977
View File
@@ -0,0 +1,977 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:30:30 08/27/2006
-- Design Name:
-- Module Name: ac97_test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.fixed_pkg.all;
use work.mix_pkg.all;
use work.cpu_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ac97_test is
Port (
sys_rst_n_in : in std_logic;
sys_clk_in : in std_logic;
sys_btn : in std_logic_vector(4 downto 0);
sys_dip : in std_logic_vector(7 downto 0);
sys_led : out std_logic_vector(8 downto 0);
sys_rx : in std_logic;
sys_tx : out std_logic;
sys_lcd_d : inout std_logic_vector(3 downto 0);
sys_lcd_e : out std_logic;
sys_lcd_rs : out std_logic;
sys_lcd_rw : out std_logic;
ac97_bit_clk : in STD_LOGIC;
ac97_sdata_in : in STD_LOGIC;
ac97_reset_n : out STD_LOGIC;
ac97_sdata_out : out STD_LOGIC;
ac97_sync : out STD_LOGIC
);
end ac97_test;
architecture Behavioral of ac97_test is
constant mix_nbits : integer := 18;
constant nco_nbits_wave : integer := 18;
constant nco_nbits_phase : integer := 16;
constant fir_bp_nbits : integer := 18;
constant fir_lp_nbits : integer := 18;
constant f : REAL := 1.0E3;
constant df : REAL := 100.0;
constant fa : REAL := 48.0E3;
constant nco_freq_word : integer := integer(f/fa*2.0**nco_nbits_phase);
constant nco_freq_inc : integer := integer(df/fa*2.0**nco_nbits_phase);
type stereo_t is (left, right);
type pcm_data_t is array (stereo_t) of signed(17 downto 0);
type stereo_bits_t is array (stereo_t) of std_logic;
------------------------------------------------------------------
COMPONENT singleshot
GENERIC (mode : integer);
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
COMPONENT ac_io
Port (
rst : in std_logic;
clk : in std_logic;
ready : out std_logic;
sync_strobe : out unsigned(0 to 2);
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
rx_pcm_addr : in unsigned (3 downto 0);
rx_pcm_data : out unsigned (19 downto 0);
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
tx_pcm_addr : in unsigned(3 downto 0);
tx_pcm_data : in unsigned(19 downto 0);
tx_pcm_we : in std_logic;
ac_sdata_in : in std_logic;
ac_bit_clk : in std_logic;
ac_reset_n : out std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
SIGNAL sync_strobe : unsigned(0 to 2);
SIGNAL slot_valid : unsigned(0 to 12);
SIGNAL cmd_we : std_logic;
SIGNAL cmd_addr : unsigned(19 downto 0);
SIGNAL cmd_data : unsigned(19 downto 0);
SIGNAL stat_addr : unsigned(19 downto 0);
SIGNAL stat_data : unsigned(19 downto 0);
SIGNAL tx_pcm_addr : unsigned(3 downto 0);
SIGNAL tx_pcm_data : unsigned(19 downto 0);
SIGNAL rx_pcm_addr : unsigned(3 downto 0);
SIGNAL tx_pcm_we : std_logic;
SIGNAL rx_pcm_data : unsigned(19 downto 0);
COMPONENT syn_nco
PORT(
rst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nco_nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nco_nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nco_nbits_phase-1 downto 0);
wave_out_i : out signed(nco_nbits_wave-1 downto 0);
wave_out_q : out signed(nco_nbits_wave-1 downto 0);
out_valid : out std_logic
);
END COMPONENT;
SIGNAL nco_pacc_clr : std_logic;
SIGNAL nco_pacc_inc : std_logic;
SIGNAL nco_freq_in : unsigned(nco_nbits_phase-1 downto 0);
SIGNAL nco_freq_load : std_logic;
SIGNAL nco_phase_in : unsigned(nco_nbits_phase-1 downto 0);
SIGNAL nco_phase_load : std_logic;
SIGNAL nco_phase_out : unsigned(nco_nbits_phase-1 downto 0);
signal pcm_nco_data : pcm_data_t;
SIGNAL nco_out_valid : std_logic;
COMPONENT cpu_embedded
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
int_in : in STD_LOGIC;
int_ack : out STD_LOGIC;
xmem_we : out STD_LOGIC;
xmem_re : out STD_LOGIC;
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
io_sel : out STD_LOGIC
);
END COMPONENT;
signal cpu_ce : std_logic;
signal cpu_int_in : std_logic;
signal cpu_int_ack : std_logic;
signal cpu_din : dmem_data_t;
signal cpu_dout : dmem_data_t;
signal cpu_addr : dmem_addr_t;
signal cpu_we : std_logic;
signal cpu_re : std_logic;
signal cpu_io_sel : std_logic;
COMPONENT xrom
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in dmem_addr_t;
dout : out dmem_data_t
);
END COMPONENT;
signal xrom_data : dmem_data_t;
COMPONENT syn_fir_bandpass
PORT(
rst : in std_logic;
clk : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(fir_bp_nbits-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(fir_bp_nbits-1 downto 0);
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(fir_bp_nbits-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(fir_bp_nbits-1 downto 0)
);
END COMPONENT;
signal fir_bp_ready : stereo_bits_t;
signal fir_bp_din_we : stereo_bits_t;
signal fir_bp_dout_valid : stereo_bits_t;
signal fir_bp_din : pcm_data_t;
signal fir_bp_dout : pcm_data_t;
COMPONENT syn_fir_lowpass
PORT(
rst : in std_logic;
clk : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(fir_lp_nbits-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(fir_lp_nbits-1 downto 0);
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(fir_lp_nbits-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(fir_lp_nbits-1 downto 0)
);
END COMPONENT;
signal fir_lp_ready : stereo_bits_t;
signal fir_lp_din_we : stereo_bits_t;
signal fir_lp_dout_valid : stereo_bits_t;
signal fir_lp_din : pcm_data_t;
signal fir_lp_dout : pcm_data_t;
COMPONENT mix_cpx
GENERIC
(
nbits_in : integer;
nbits_in_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
nbits_scale_z : integer;
has_in_reg : boolean;
has_pipe_reg : boolean;
has_out_reg : boolean;
rounding : boolean;
saturating : boolean
);
PORT
(
srst : in std_logic;
clk : in std_logic;
in_valid : in std_logic;
x_re_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
x_im_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
y_re_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
y_im_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
out_valid : out std_logic;
z_re_out : out sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
z_im_out : out sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low)
);
END COMPONENT;
constant mix_nbits_scale_z : integer := 1;
signal mix_x_re : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
signal mix_x_im : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
signal mix_y_re : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
signal mix_y_im : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
signal mix_z_re : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
signal mix_z_im : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
signal mix_in_valid : std_logic;
signal mix_out_valid : std_logic;
COMPONENT lcd_port
PORT (
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout std_logic_vector(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
END COMPONENT;
signal cpu_lcd_in_reg, cpu_lcd_out_reg : unsigned(DMEM_DATA_WIDTH-1 downto 0);
signal cpu_lcd_we : std_logic;
------------------------------------------------------------------
-- X"1F400", -- W: DAC rate 8000Hz
-- X"AC440", -- W: DAC rate 44100Hz
------------------------------------------------------------------
type state_t is (st_reset, st_pcm_in, st_pcm_in3, st_pcm_in4, st_pcm_out, st_pcm_out3, st_pcm_out4);
signal rst, clk : std_logic;
signal acio_ready : std_logic;
signal nco_freq_set : unsigned(nco_nbits_phase-1 downto 0);
signal pcm_rom_data : signed(19 downto 0);
signal pcm_rom_addr : unsigned(9 downto 0);
signal pcm_active, cmd_active : std_logic;
signal state, nextstate : state_t;
signal ac_reset_n : std_logic;
signal ac_rst : std_logic;
signal ac_ssync : std_logic;
signal pcm_request, pcm_request_set, pcm_request_ack : std_logic;
signal started_up : std_logic := '1';
signal cpu_freq, cpu_cmd_addr, cpu_cmd_data, cpu_stat_addr, cpu_stat_data : unsigned(15 downto 0);
signal cpu_mix_dc_adj_left, cpu_mix_dc_adj_right, cpu_pcmin_dc_adj_left, cpu_pcmin_dc_adj_right : unsigned(15 downto 0);
subtype low is unsigned(7 downto 0);
subtype high is unsigned(15 downto 8);
signal pcm_in_data : pcm_data_t;
signal pcm_out_data : pcm_data_t;
signal pcm_in_data_we, pcm_in_valid : stereo_bits_t;
type pcmout_mode_t is (PCMOUT_TONE, PCMOUT_LOOPTHROUGH, PCMOUT_FILTERED, PCMOUT_MIXER, PCMOUT_FM, PCMOUT_BASEBAND);
signal pcmout_mode : pcmout_mode_t;
signal pcm_table_data : unsigned(19 downto 0);
signal cpu_cmd_access, cpu_freq_access, cpu_cmd_ready, cpu_stat_ready : std_logic;
signal cpu_led_reg, cpu_btn_reg, cpu_dip_reg, cpu_pcmmode_reg : unsigned(DMEM_DATA_WIDTH-1 downto 0);
signal cpu_cmd_we, cmd_access_is_fsm : std_logic;
------------------------------------------------------------------
function GetRequest(slot1 : unsigned) return unsigned is
variable res : unsigned(3 to 12);
begin
res := (others => '0');
for i in res'range loop
res(i) := not slot1(14-i);
end loop;
return res;
end GetRequest;
begin
------------------------------------------------------------------
cmd_data <= (cpu_cmd_data & "0000");
cmd_addr <= (cpu_cmd_addr & "0000");
ac_rst <= not ac_reset_n;
ac97_reset_n <= ac_reset_n;
ac97_sync <= ac_ssync;
sys_tx <= sys_rx;
cpu_ce <= '1';
clk <= sys_clk_in;
rst <= not (started_up and sys_rst_n_in);
-- rst <= not (sys_rst_n_in);
cpu_int_in <= sync_strobe(0);
fir_bp_din_we(left) <= pcm_in_valid(left) and fir_bp_ready(left);
fir_bp_din_we(right) <= pcm_in_valid(right) and fir_bp_ready(right);
fir_bp_din(left to right) <= pcm_in_data(left to right);
fir_lp_din_we(left) <= mix_out_valid and fir_lp_ready(left);
fir_lp_din_we(right) <= mix_out_valid and fir_lp_ready(right);
fir_lp_din(left) <= to_signed(mix_z_re);
fir_lp_din(right) <= to_signed(mix_z_im);
------------------------------------------------------------------
proc_led_btn:
process (rst, clk)
begin
if rising_edge(clk) then
cpu_btn_reg <= "000" & unsigned(sys_btn);
cpu_dip_reg <= unsigned(sys_dip);
if rst = '1' then
sys_led <= (others => '0');
else
sys_led(7 downto 0) <= STD_LOGIC_VECTOR(cpu_led_reg);
end if;
end if;
end process;
------------------------------------------------------------------
host_din : process (acio_ready, sync_strobe, slot_valid, stat_addr, state, pcm_request, pcm_out_data)
variable request : unsigned(3 to 12);
variable rx_frame_valid : std_logic;
variable sync_frame, sync_status, sync_tx : std_logic;
begin
request := GetRequest(stat_addr);
rx_frame_valid := slot_valid(0);
sync_frame := sync_strobe(0);
sync_status := sync_strobe(1);
sync_tx := sync_strobe(2);
tx_pcm_we <= '0';
tx_pcm_addr <= to_unsigned(3, tx_pcm_addr'length);
tx_pcm_data <= to_unsigned(0, tx_pcm_data'length);
rx_pcm_addr <= to_unsigned(3, rx_pcm_addr'length);
nextstate <= state;
pcm_active <= '0';
cmd_active <= '0';
pcm_request_set <= '0';
pcm_request_ack <= '0';
pcm_in_data_we <= (others => '0');
nco_pacc_inc <= '0';
nco_pacc_clr <= '0';
nco_phase_in <= (others => '0');
nco_phase_load <= '0';
case state is
when st_reset =>
if rx_frame_valid = '1' and sync_status = '1' and acio_ready = '1' then
nextstate <= st_pcm_in;
end if;
when st_pcm_in =>
if rx_frame_valid = '1' and sync_frame = '1' then
nextstate <= st_pcm_in3;
end if;
when st_pcm_in3 =>
nextstate <= st_pcm_in4;
rx_pcm_addr <= to_unsigned(3, rx_pcm_addr'length);
if slot_valid(3) = '1' then
pcm_in_data_we(left) <= '1';
end if;
when st_pcm_in4 =>
nextstate <= st_pcm_out;
rx_pcm_addr <= to_unsigned(4, rx_pcm_addr'length);
if slot_valid(4) = '1' then
pcm_in_data_we(right) <= '1';
end if;
when st_pcm_out =>
pcm_active <= '1';
if rx_frame_valid = '1' and sync_status = '1' then
if request(3) = '1' and request(4) = '1' then
pcm_request_set <= '1';
nco_pacc_inc <= '1';
end if;
end if;
if pcm_request = '1' and sync_tx = '1' then
nextstate <= st_pcm_out3;
end if;
when st_pcm_out3 =>
tx_pcm_data <= unsigned(pcm_out_data(left)) & "00";
pcm_active <= '1';
tx_pcm_addr <= to_unsigned(3, tx_pcm_addr'length);
tx_pcm_we <= '1';
pcm_request_ack <= '1';
nextstate <= st_pcm_out4;
when st_pcm_out4 =>
tx_pcm_data <= unsigned(pcm_out_data(right)) & "00";
pcm_active <= '1';
tx_pcm_addr <= to_unsigned(4, tx_pcm_addr'length);
tx_pcm_we <= '1';
nextstate <= st_pcm_in;
when others =>
nextstate <= st_reset;
end case;
end process;
proc_fsm_next:
process (rst, clk, nextstate)
begin
if rst = '1' then
state <= st_reset;
elsif rising_edge(clk) then
state <= nextstate;
end if;
end process;
-------------------------------------------------------------
-- proc_pcm_in
-------------------------------------------------------------
proc_pcm_in:
process (rst, clk, pcm_in_data_we, rx_pcm_data)
variable dc_adj : pcm_data_t;
begin
dc_adj(left) := resize(signed(cpu_pcmin_dc_adj_left), dc_adj(left)'length);
dc_adj(right) := resize(signed(cpu_pcmin_dc_adj_right), dc_adj(right)'length);
if rst = '1' then
for i in pcm_in_data'range loop
dc_adj(i) := (others => '0');
pcm_in_data(i) <= (others => '0');
pcm_in_valid(i) <= '0';
end loop;
elsif rising_edge(clk) then
for i in pcm_in_data'range loop
pcm_in_valid(i) <= '0';
end loop;
for i in pcm_in_data'range loop
if pcm_in_data_we(i) = '1' then
pcm_in_valid(i) <= '1';
pcm_in_data(i) <= dc_adj(i) + signed(rx_pcm_data(19 downto 2));
end if;
end loop;
end if;
end process;
-------------------------------------------------------------
-- proc_mix_input
-------------------------------------------------------------
proc_mix_input:
process (rst, clk)
begin
if rst = '1' then
mix_in_valid <= '0';
mix_x_re <= to_sfixed(0.0, mix_x_re);
mix_x_im <= to_sfixed(0.0, mix_x_im);
elsif rising_edge(clk) then
mix_in_valid <= '0';
if fir_bp_dout_valid(right) = '1' then
mix_in_valid <= '1';
mix_x_re <= sfixed(signed(cpu_mix_dc_adj_left) + fir_bp_dout(left));
mix_x_im <= sfixed(signed(cpu_mix_dc_adj_right) + fir_bp_dout(right));
end if;
mix_y_re <= sfixed(pcm_nco_data(left));
mix_y_im <= sfixed(pcm_nco_data(right));
end if;
end process;
-------------------------------------------------------------
-- proc_pcmout_mode_mapper
-------------------------------------------------------------
proc_pcmout_mode_mapper:
process (cpu_pcmmode_reg)
begin
case cpu_pcmmode_reg is
when X"00" =>
pcmout_mode <= PCMOUT_LOOPTHROUGH;
when X"01" =>
pcmout_mode <= PCMOUT_FILTERED;
when X"02" =>
pcmout_mode <= PCMOUT_TONE;
when X"03" =>
pcmout_mode <= PCMOUT_MIXER;
when X"04" =>
pcmout_mode <= PCMOUT_FM;
when X"05" =>
pcmout_mode <= PCMOUT_BASEBAND;
when others =>
pcmout_mode <= PCMOUT_LOOPTHROUGH;
end case;
end process;
-------------------------------------------------------------
-- proc_pcm_out_mux
-------------------------------------------------------------
proc_pcm_out_mux:
process (clk)
begin
if rising_edge(clk) then
case pcmout_mode is
when PCMOUT_TONE | PCMOUT_FM =>
pcm_out_data(left to right) <= pcm_nco_data(left to right);
when PCMOUT_LOOPTHROUGH =>
pcm_out_data(left to right) <= pcm_in_data(left to right);
when PCMOUT_FILTERED =>
pcm_out_data(left to right) <= fir_bp_dout(left to right);
when PCMOUT_MIXER =>
pcm_out_data(left) <= to_signed(mix_z_re);
pcm_out_data(right) <= to_signed(mix_z_im);
when PCMOUT_BASEBAND =>
pcm_out_data(left to right) <= fir_lp_dout(left to right);
when others =>
pcm_out_data(left to right) <= pcm_nco_data(left to right);
end case;
end if;
end process;
-------------------------------------------------------------
-- proc_freq_mod
-------------------------------------------------------------
proc_freq_mod:
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
nco_freq_set <= to_unsigned(nco_freq_word, nco_nbits_phase);
elsif cpu_freq_access = '1' then
nco_freq_set <= cpu_freq;
end if;
if pcmout_mode = PCMOUT_FM then
nco_freq_in <= unsigned(fir_bp_dout(left)(nco_freq_in'left downto 2) + signed(nco_freq_set));
else
nco_freq_in <= nco_freq_set;
end if;
nco_freq_load <= fir_bp_dout_valid(left);
end if;
end process;
-------------------------------------------------------------
-- proc_cpu_flags
-------------------------------------------------------------
proc_cpu_stat_reg_control:
process (clk, sync_strobe, slot_valid)
variable rx_frame_valid : std_logic;
variable sync_frame, sync_status, sync_tx : std_logic;
begin
rx_frame_valid := slot_valid(0);
sync_frame := sync_strobe(0);
sync_status := sync_strobe(1);
sync_tx := sync_strobe(2);
if rising_edge(clk) then
if rst = '1' then
cpu_cmd_ready <= '0';
cpu_stat_ready <= '0';
cpu_stat_addr <= (others => '0');
cpu_stat_data <= (others => '0');
else
cpu_cmd_we <= '0';
if cpu_cmd_access = '1' then
cpu_cmd_ready <= '0';
cpu_stat_ready <= '0';
end if;
if cpu_cmd_ready = '0' then
if sync_tx = '1' and rx_frame_valid = '1' then
cpu_cmd_we <= '1';
cpu_cmd_ready <= '1';
end if;
end if;
if sync_status = '1' and slot_valid(0 to 2) = "111" then
cpu_stat_ready <= '1';
cpu_stat_addr <= stat_addr(19 downto 4);
cpu_stat_data <= stat_data(19 downto 4);
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_cpu_dout_reg
-------------------------------------------------------------
proc_cpu_dout_reg:
process (clk)
variable addr : dmem_addr_t;
begin
if rising_edge(clk) then
if rst = '1' then
cpu_led_reg <= (others => '0');
cpu_pcmmode_reg <= (others => '0');
cpu_freq <= (others => '0');
cpu_cmd_addr <= (others => '0');
cpu_cmd_data <= (others => '0');
cpu_lcd_out_reg <= (others => '0');
cpu_mix_dc_adj_left <= (others => '0');
cpu_mix_dc_adj_right <= (others => '0');
cpu_pcmin_dc_adj_left <= (others => '0');
cpu_pcmin_dc_adj_right <= (others => '0');
else
addr := cpu_addr;
cpu_cmd_access <= '0';
cpu_freq_access <= '0';
cpu_lcd_we <= '0';
if cpu_we = '1' and cpu_io_sel = '1' then
case addr is
when X"00" =>
cpu_led_reg <= cpu_dout;
when X"01" =>
cpu_pcmmode_reg <= cpu_dout;
when X"02" =>
cpu_freq_access <= '1';
cpu_freq(low'range) <= cpu_dout;
when X"03" =>
cpu_freq(high'range) <= cpu_dout;
when X"04" =>
cpu_cmd_addr(low'range) <= cpu_dout;
when X"05" =>
cpu_cmd_addr(high'range) <= cpu_dout;
when X"06" =>
cpu_cmd_access <= '1';
cpu_cmd_data(low'range) <= cpu_dout;
when X"07" =>
cpu_cmd_data(high'range) <= cpu_dout;
when X"08" =>
cpu_lcd_we <= '1';
cpu_lcd_out_reg <= cpu_dout;
when X"09" =>
cpu_mix_dc_adj_left(low'range) <= cpu_dout;
when X"0A" =>
cpu_mix_dc_adj_left(high'range) <= cpu_dout;
when X"0B" =>
cpu_mix_dc_adj_right(low'range) <= cpu_dout;
when X"0C" =>
cpu_mix_dc_adj_right(high'range) <= cpu_dout;
when X"0D" =>
cpu_pcmin_dc_adj_left(low'range) <= cpu_dout;
when X"0E" =>
cpu_pcmin_dc_adj_left(high'range) <= cpu_dout;
when X"0F" =>
cpu_pcmin_dc_adj_right(low'range) <= cpu_dout;
when X"10" =>
cpu_pcmin_dc_adj_right(high'range) <= cpu_dout;
when others => null;
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_cpu_din_reg
-------------------------------------------------------------
proc_cpu_din_reg:
process (clk, cpu_io_sel, xrom_data)
variable mix_xre, mix_xim : signed (mix_nbits-1 downto 0);
variable mix_yre, mix_yim : signed (mix_nbits-1 downto 0);
variable addr : dmem_addr_t;
begin
mix_xre := to_signed(mix_x_re);
mix_xim := to_signed(mix_x_im);
mix_yre := to_signed(mix_y_re);
mix_yim := to_signed(mix_y_im);
if rising_edge(clk) then
addr := cpu_addr;
end if;
if cpu_io_sel = '0' then
cpu_din <= xrom_data;
else
case addr is
when X"00" =>
cpu_din <= cpu_led_reg;
when X"01" =>
cpu_din <= cpu_pcmmode_reg;
when X"02" =>
cpu_din <= cpu_freq(low'range);
when X"03" =>
cpu_din <= cpu_freq(high'range);
when X"04" =>
cpu_din <= cpu_stat_addr(low'range);
when X"05" =>
cpu_din <= cpu_stat_addr(high'range);
when X"06" =>
cpu_din <= cpu_stat_data(low'range);
when X"07" =>
cpu_din <= cpu_stat_data(high'range);
when X"08" =>
cpu_din <= cpu_lcd_in_reg;
when X"09" =>
cpu_din <= cpu_mix_dc_adj_left(low'range);
when X"0A" =>
cpu_din <= cpu_mix_dc_adj_left(high'range);
when X"0B" =>
cpu_din <= cpu_mix_dc_adj_right(low'range);
when X"0C" =>
cpu_din <= cpu_mix_dc_adj_right(high'range);
when X"0D" =>
cpu_din <= cpu_pcmin_dc_adj_left(low'range);
when X"0E" =>
cpu_din <= cpu_pcmin_dc_adj_left(high'range);
when X"0F" =>
cpu_din <= cpu_pcmin_dc_adj_right(low'range);
when X"10" =>
cpu_din <= cpu_pcmin_dc_adj_right(high'range);
when X"80" =>
cpu_din <= cpu_btn_reg;
when X"81" =>
cpu_din <= cpu_dip_reg;
when X"82" =>
cpu_din <= dmem_data_t(pcm_in_data(left)(low'range));
when X"83" =>
cpu_din <= dmem_data_t(pcm_in_data(left)(high'range));
when X"84" =>
cpu_din <= dmem_data_t(pcm_in_data(right)(low'range));
when X"85" =>
cpu_din <= dmem_data_t(pcm_in_data(right)(high'range));
when X"86" =>
cpu_din <= dmem_data_t(mix_xre(low'range));
when X"87" =>
cpu_din <= dmem_data_t(mix_xre(high'range));
when X"88" =>
cpu_din <= dmem_data_t(mix_xim(low'range));
when X"89" =>
cpu_din <= dmem_data_t(mix_xim(high'range));
when X"8A" =>
cpu_din <= dmem_data_t(mix_yre(low'range));
when X"8B" =>
cpu_din <= dmem_data_t(mix_yre(high'range));
when X"8C" =>
cpu_din <= dmem_data_t(mix_yim(low'range));
when X"8D" =>
cpu_din <= dmem_data_t(mix_yim(high'range));
when X"A0" =>
cpu_din <= "0000" & (fir_bp_ready(left) and fir_bp_ready(right)) & cpu_stat_ready & cpu_cmd_ready & (pcm_active and acio_ready and slot_valid(0));
when others =>
if addr(0) = '0' then
cpu_din <= X"EF";
else
cpu_din <= X"BE";
end if;
end case;
end if;
end process;
-------------------------------------------------------------
proc_pcm_request:
process (clk, pcm_request_set, pcm_request_ack)
begin
if rising_edge(clk) then
if pcm_request_ack = '1' or rst = '1' then
pcm_request <= '0';
elsif pcm_request_set = '1' then
pcm_request <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
-- Instantiate the Unit Under Test (UUT)
inst_ac_io: ac_io PORT MAP(
rst => rst,
clk => clk,
ready => acio_ready,
sync_strobe => sync_strobe,
slot_valid => slot_valid,
stat_addr => stat_addr,
stat_data => stat_data,
rx_pcm_addr => rx_pcm_addr,
rx_pcm_data => rx_pcm_data,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cpu_cmd_we,
tx_pcm_addr => tx_pcm_addr,
tx_pcm_data => tx_pcm_data,
tx_pcm_we => tx_pcm_we,
ac_sdata_in => ac97_sdata_in,
ac_bit_clk => ac97_bit_clk,
ac_reset_n => ac_reset_n,
ac_sdata_out => ac97_sdata_out,
ac_ssync => ac_ssync
);
inst_syn_nco: syn_nco
PORT MAP(
rst => rst,
clk => clk,
pacc_clr => nco_pacc_clr,
pacc_inc => nco_pacc_inc,
freq_in => nco_freq_in,
freq_load => nco_freq_load,
phase_in => nco_phase_in,
phase_load => nco_phase_load,
phase_out => nco_phase_out,
wave_out_i => pcm_nco_data(left),
wave_out_q => pcm_nco_data(right),
out_valid => nco_out_valid
);
inst_cpu_embedded: cpu_embedded
PORT MAP(
rst => rst,
clk => clk,
ce => cpu_ce,
int_in => cpu_int_in,
int_ack => cpu_int_ack,
xmem_we => cpu_we,
xmem_re => cpu_re,
xmem_din => cpu_din,
xmem_dout => cpu_dout,
xmem_addr => cpu_addr,
io_sel => cpu_io_sel
);
inst_xrom: xrom
PORT MAP(
clk => clk,
ce => cpu_ce,
addr => cpu_addr,
dout => xrom_data
);
inst_syn_fir_bandpass: syn_fir_bandpass
PORT MAP(
rst => rst,
clk => clk,
ready_i => fir_bp_ready(left),
x_valid_i => fir_bp_din_we(left),
x_din_i => fir_bp_din(left),
y_valid_i => fir_bp_dout_valid(left),
y_dout_i => fir_bp_dout(left),
ready_q => fir_bp_ready(right),
x_valid_q => fir_bp_din_we(right),
x_din_q => fir_bp_din(right),
y_valid_q => fir_bp_dout_valid(right),
y_dout_q => fir_bp_dout(right)
);
inst_syn_fir_lowpass: syn_fir_lowpass
PORT MAP(
rst => rst,
clk => clk,
ready_i => fir_lp_ready(left),
x_valid_i => fir_lp_din_we(left),
x_din_i => fir_lp_din(left),
y_valid_i => fir_lp_dout_valid(left),
y_dout_i => fir_lp_dout(left),
ready_q => fir_lp_ready(right),
x_valid_q => fir_lp_din_we(right),
x_din_q => fir_lp_din(right),
y_valid_q => fir_lp_dout_valid(right),
y_dout_q => fir_lp_dout(right)
);
inst_mix_cpx: mix_cpx
GENERIC MAP
(
nbits_in => mix_nbits,
nbits_in_frac => mix_nbits,
nbits_out => mix_nbits,
nbits_out_frac => mix_nbits,
nbits_scale_z => mix_nbits_scale_z,
has_in_reg => true,
has_pipe_reg => true,
has_out_reg => true,
rounding => false,
saturating => false
)
PORT MAP
(
srst => rst,
clk => clk,
in_valid => mix_in_valid,
x_re_in => mix_x_re,
x_im_in => mix_x_im,
y_re_in => mix_y_re,
y_im_in => mix_y_im,
out_valid => mix_out_valid,
z_re_out => mix_z_re,
z_im_out => mix_z_im
);
inst_lcd_port: lcd_port
PORT MAP(
rst => rst,
clk => clk,
we => cpu_lcd_we,
din => cpu_lcd_out_reg,
dout => cpu_lcd_in_reg,
lcd_d => sys_lcd_d,
lcd_e => sys_lcd_e,
lcd_rs => sys_lcd_rs,
lcd_rw => sys_lcd_rw
);
------------------------------------------------------------------
STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4
port map (
EOS => started_up, -- End of Startup 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => '0', -- USRCCLKO 1-bit input
USRCCLKTS => '0', -- USRCCLKTS 1-bit input
USRDONEO => '0', -- USRDONEO 1-bit input
USRDONETS => '0' -- USRDONETS 1-bit input
);
------------------------------------------------------------------
end Behavioral;
projects/ac97_Controller/src/ac_in.vhd
+309
View File
@@ -0,0 +1,309 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:27:43 08/26/2006
-- Design Name:
-- Module Name: ac_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ac_in is
Port (
rst : in std_logic;
clk : in std_logic;
sync_frame : out std_logic;
sync_status : out std_logic;
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
pcm_out_addr : in unsigned (3 downto 0);
pcm_out_data : out unsigned (19 downto 0);
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_in : in std_logic;
ac_ssync : in std_logic
);
end ac_in;
architecture Behavioral of ac_in is
------------------------------------------------------------------
COMPONENT singleshot
GENERIC (mode : integer);
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------
type sac_t is (ac_idle, ac_tag, ac_data);
subtype bitcnt_t is integer range 0 to 19;
subtype slotcnt_t is integer range 0 to 12;
subtype slot_valid_t is UNSIGNED(0 to 12);
subtype tag_t is UNSIGNED(15 downto 0);
subtype slot_t is UNSIGNED(19 downto 0);
type slot_array_t is array (natural range <>) of slot_t;
signal data_array : slot_array_t (1 to 12);
signal tag : tag_t;
signal sac, snac : sac_t;
signal bitcnt : bitcnt_t;
signal bitcnt_rst, bitcnt_en : STD_LOGIC;
signal slotcnt : slotcnt_t;
signal slotcnt_rst, slotcnt_en : STD_LOGIC;
signal rx_reg : slot_t;
signal stat_read, host_update : STD_LOGIC;
signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC;
------------------------------------------------------------------
function GetSlotValid(data : tag_t) return slot_valid_t is
variable res : slot_valid_t := (others => '0');
begin
res := (others => '0');
for i in slot_valid_t'range loop
res(i) := data(data'left-i);
end loop;
return res;
end GetSlotValid;
------------------------------------------------------------------
begin
-------------------------------------------------------------
-- proc_status_flags
-------------------------------------------------------------
proc_status_flags:
process (rst, clk, host_update, tag, data_array)
begin
if rising_edge(clk) then
sync_status <= '0';
if rst = '1' then
slot_valid <= (others => '0');
stat_addr <= (others => '0');
stat_data <= (others => '0');
elsif host_update = '1' then
sync_status <= '1';
slot_valid <= GetSlotValid(tag);
stat_addr <= data_array(1);
stat_data <= data_array(2);
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_pcm_data
-------------------------------------------------------------
proc_pcm_data:
process (clk, pcm_out_addr, data_array)
variable slot_id : integer range 0 to 12;
begin
pcm_out_data <= (others => '-');
slot_id := to_integer(pcm_out_addr);
if (slot_id > 2) then
pcm_out_data <= data_array(slot_id);
end if;
end process;
-------------------------------------------------------------
-- proc_read_data
-------------------------------------------------------------
proc_read_data :
process (ac_reset, ac_bit_clk, slot_end, slotcnt)
begin
if ac_reset = '1' then
stat_read <= '0';
elsif rising_edge(ac_bit_clk) then
stat_read <= '0';
if slot_end = '1' and slotcnt /= 0 then
data_array(slotcnt) <= rx_reg;
if slotcnt = 2 then
stat_read <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_read_stat
-------------------------------------------------------------
proc_read_tag :
process (ac_reset, ac_bit_clk, sync_end)
begin
if ac_reset = '1' then
tag <= (others => '0');
elsif rising_edge(ac_bit_clk) then
if sync_end = '1' then
tag <= rx_reg(15 downto 0);
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_slot_count
-------------------------------------------------------------
proc_slot_count:
process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
begin
if rising_edge(ac_bit_clk) then
if slotcnt_rst = '1' then
slotcnt <= slotcnt_t'low;
elsif slotcnt_en = '1' then
if slotcnt /= slotcnt_t'high then
slotcnt <= slotcnt + 1;
else
slotcnt <= slotcnt_t'low;
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_bit_count
-------------------------------------------------------------
proc_bit_count:
process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
begin
if rising_edge(ac_bit_clk) then
if bitcnt_rst = '1' then
bitcnt <= bitcnt_t'low;
elsif bitcnt_en = '1' then
if bitcnt /= bitcnt_t'high then
bitcnt <= bitcnt + 1;
else
bitcnt <= bitcnt_t'low;
end if;
end if;
end if;
end process;
------------------------------------------------------------------
proc_ac_fsm:
process (bitcnt, slotcnt, sac, ac_ssync)
begin
snac <= sac;
bitcnt_rst <= '0';
bitcnt_en <= '1';
slotcnt_rst <= '0';
slotcnt_en <= '0';
slot_end <= '0';
sync_end <= '0';
last_slot <= '0';
start_of_frame <= '0';
if bitcnt = 19 then
slot_end <= '1';
end if;
if slotcnt = 12 and bitcnt = 19 then
last_slot <= '1';
end if;
case sac is
when ac_idle =>
bitcnt_rst <= '1';
slotcnt_rst <= '1';
if (ac_ssync = '1') then
snac <= ac_tag;
end if;
when ac_tag =>
if (bitcnt = 0) then
start_of_frame <= '1';
elsif (bitcnt = 15) then
slotcnt_en <= '1';
bitcnt_rst <= '1';
sync_end <= '1';
if (ac_ssync = '0') then
snac <= ac_data;
else
snac <= ac_idle;
end if;
end if;
when ac_data =>
if bitcnt = 19 then
slotcnt_en <= '1';
if slotcnt = 12 then
slotcnt_rst <= '1';
snac <= ac_tag;
end if;
end if;
when others => null;
end case;
end process;
proc_ac_fsm_next:
process (ac_reset, ac_bit_clk, snac)
begin
if ac_reset = '1' then
sac <= ac_idle;
elsif rising_edge(ac_bit_clk) then
sac <= snac;
end if;
end process;
-------------------------------------------------------------
-- Receive Shift Register
-------------------------------------------------------------
process (ac_reset, ac_bit_clk, ac_sdata_in)
begin
if ac_reset = '1' then
rx_reg <= (others => '0');
elsif falling_edge(ac_bit_clk) then
rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in;
end if;
end process;
------------------------------------------------------------------
singleshot_inst1: singleshot
GENERIC MAP (
mode => 0)
PORT MAP(
rst => rst,
clk => clk,
input => stat_read,
output => host_update
);
singleshot_inst2: singleshot
GENERIC MAP (
mode => 1)
PORT MAP(
rst => rst,
clk => clk,
input => start_of_frame,
output => sync_frame
);
-------------------------------------------------------------
end Behavioral;
projects/ac97_Controller/src/ac_io.vhd
+189
View File
@@ -0,0 +1,189 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:29:55 08/26/2006
-- Design Name:
-- Module Name: ac_io - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ac_io is
Port
(
rst : in std_logic;
clk : in std_logic;
ready : out std_logic;
sync_strobe : out unsigned(0 to 2);
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
rx_pcm_addr : in unsigned (3 downto 0);
rx_pcm_data : out unsigned (19 downto 0);
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
tx_pcm_addr : in unsigned(3 downto 0);
tx_pcm_data : in unsigned(19 downto 0);
tx_pcm_we : in std_logic;
ac_sdata_in : in std_logic;
ac_bit_clk : in std_logic;
ac_reset_n : out std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
end ac_io;
architecture Behavioral of ac_io is
COMPONENT ac_in
Port
(
rst : in std_logic;
clk : in std_logic;
sync_frame : out std_logic;
sync_status : out std_logic;
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
pcm_out_addr : in unsigned (3 downto 0);
pcm_out_data : out unsigned (19 downto 0);
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_in : in std_logic;
ac_ssync : in std_logic
);
END COMPONENT;
COMPONENT ac_out
PORT
(
rst : in std_logic;
clk : in std_logic;
sync_tx : out std_logic;
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
pcm_in_addr : in unsigned(3 downto 0);
pcm_in_data : in unsigned(19 downto 0);
pcm_in_we : in std_logic;
ac_bit_clk : in std_logic;
ac_reset : in std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
SIGNAL ac_reset : std_logic;
SIGNAL ssync_rx : std_logic;
SIGNAL ssync_tx : std_logic;
SIGNAL sync_frame : std_logic;
SIGNAL sync_status : std_logic;
SIGNAL sync_tx : std_logic;
begin
inst_ac_in: ac_in
PORT MAP
(
rst => rst,
clk => clk,
sync_frame => sync_frame,
sync_status => sync_status,
slot_valid => slot_valid,
stat_addr => stat_addr,
stat_data => stat_data,
pcm_out_addr => rx_pcm_addr,
pcm_out_data => rx_pcm_data,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_in => ac_sdata_in,
ac_ssync => ssync_rx
);
inst_ac_out: ac_out
PORT MAP
(
rst => rst,
clk => clk,
sync_tx => sync_tx,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
pcm_in_addr => tx_pcm_addr,
pcm_in_data => tx_pcm_data,
pcm_in_we => tx_pcm_we,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_out => ac_sdata_out,
ac_ssync => ssync_tx
);
------------------------------------------------------------------
ready <= not ac_reset;
ac_ssync <= ssync_tx;
ssync_rx <= ssync_tx;
sync_strobe <= sync_frame & sync_status & sync_tx;
------------------------------------------------------------------
proc_reset_gen:
process (rst, clk, ac_bit_clk)
type rstate_t is (s0, s1);
variable rstate, rstaten : rstate_t;
subtype cnt_t is integer range 0 to 999;
variable cnt : cnt_t;
begin
if rising_edge(clk) then
if rst = '1' then
rstate := s0;
cnt := cnt_t'high;
ac_reset <= '1';
ac_reset_n <= '0';
else
rstaten := rstate;
case rstate is
when s0 =>
if cnt /= 0 then
cnt := cnt - 1;
else
ac_reset_n <= '1';
if ac_bit_clk = '1' then
rstaten := s1;
cnt := cnt_t'high;
end if;
end if;
when s1 =>
if cnt /= 0 then
cnt := cnt - 1;
else
ac_reset <= '0';
end if;
end case;
rstate := rstaten;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
projects/ac97_Controller/src/ac_out.vhd
+276
View File
@@ -0,0 +1,276 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:12 06/05/2007
-- Design Name:
-- Module Name: ac_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ac_out is
Port (
rst : in std_logic;
clk : in std_logic;
sync_tx : out std_logic;
cmd_addr : in unsigned (19 downto 0);
cmd_data : in unsigned (19 downto 0);
cmd_we : in std_logic;
pcm_in_addr : in unsigned (3 downto 0);
pcm_in_data : in unsigned (19 downto 0);
pcm_in_we : in std_logic;
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
end ac_out;
architecture Behavioral of ac_out is
------------------------------------------------------------------
COMPONENT singleshot
GENERIC (mode : integer);
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------
subtype tag_t is UNSIGNED(15 downto 0);
subtype slot_valid_t is UNSIGNED(1 to 12);
signal slot_valid : slot_valid_t;
subtype slot_t is UNSIGNED(19 downto 0);
type slot_array_t is array (natural range <>) of slot_t;
signal data_array : slot_array_t (1 to 12);
signal tx_reg : UNSIGNED(19 downto 0);
signal last_slot, ssync : STD_LOGIC;
type sac_t is (ac_idle, ac_tag, ac_data);
signal sac, snac : sac_t;
subtype bitcnt_t is integer range 0 to 19;
subtype slotcnt_t is integer range 0 to 12;
signal bitcnt : bitcnt_t;
signal bitcnt_rst, bitcnt_en : STD_LOGIC;
signal slotcnt : slotcnt_t;
signal slotcnt_rst, slotcnt_en : STD_LOGIC;
signal slot_start : STD_LOGIC;
------------------------------------------------------------------
function CreateTag(slot_valid : slot_valid_t) return tag_t is
variable tag : tag_t := (others => '0');
begin
tag := (others => '0');
for i in slot_valid_t'range loop
tag(15-i) := slot_valid(i);
if slot_valid(i) = '1' then
tag(15) := '1';
end if;
end loop;
tag(0) := '0'; -- ID0
tag(1) := '0'; -- ID1
tag(2) := '0'; -- Reserved
-- tag(15) := '1'; -- Frame is valid
return tag;
end CreateTag;
begin
------------------------------------------------------------------
proc_slot_reg:
process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot)
variable slot_id : integer range 0 to 12;
begin
slot_id := to_integer(pcm_in_addr);
if rising_edge(clk) then
if rst = '1' then
for i in data_array'range(1) loop
data_array(i) <= (others => '0');
end loop;
slot_valid <= (others => '0');
elsif last_slot = '1' then
slot_valid <= (others => '0');
else
if cmd_we = '1' then
slot_valid(1) <= '1';
slot_valid(2) <= '1';
data_array(1) <= cmd_addr;
data_array(2) <= cmd_data;
end if;
if pcm_in_we = '1' then
if (slot_id > 2) then
data_array(slot_id) <= pcm_in_data;
slot_valid(slot_id) <= '1';
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_slot_count
-------------------------------------------------------------
proc_slot_count:
process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
begin
if rising_edge(ac_bit_clk) then
if slotcnt_rst = '1' then
slotcnt <= slotcnt_t'low;
elsif slotcnt_en = '1' then
if slotcnt /= slotcnt_t'high then
slotcnt <= slotcnt + 1;
else
slotcnt <= slotcnt_t'low;
end if;
end if;
end if;
end process;
------------------------------------------------------------------
-- proc_bit_count
------------------------------------------------------------------
proc_bit_count:
process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
begin
if rising_edge(ac_bit_clk) then
if bitcnt_rst = '1' then
bitcnt <= bitcnt_t'low;
elsif bitcnt_en = '1' then
if bitcnt /= bitcnt_t'high then
bitcnt <= bitcnt + 1;
else
bitcnt <= bitcnt_t'low;
end if;
end if;
end if;
end process;
------------------------------------------------------------------
proc_ac_fsm:
process (bitcnt, slotcnt, sac)
begin
snac <= sac;
bitcnt_rst <= '0';
bitcnt_en <= '1';
slotcnt_rst <= '0';
slotcnt_en <= '0';
slot_start <= '0';
ssync <= '0';
if bitcnt = 0 then
slot_start <= '1';
end if;
case sac is
when ac_idle =>
bitcnt_rst <= '1';
slotcnt_rst <= '1';
snac <= ac_tag;
when ac_tag =>
ssync <= '1';
if (bitcnt = 15) then
slotcnt_en <= '1';
bitcnt_rst <= '1';
snac <= ac_data;
end if;
when ac_data =>
if bitcnt = 19 then
slotcnt_en <= '1';
if slotcnt = 12 then
slotcnt_rst <= '1';
snac <= ac_tag;
end if;
end if;
when others => null;
end case;
end process;
proc_ac_fsm_next:
process (ac_reset, ac_bit_clk, snac)
begin
if ac_reset = '1' then
sac <= ac_idle;
elsif rising_edge(ac_bit_clk) then
sac <= snac;
end if;
end process;
------------------------------------------------------------------
proc_tx_shift_reg:
process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array)
begin
if ac_reset = '1' then
tx_reg <= (others => '0');
elsif rising_edge(ac_bit_clk) then
last_slot <= '0';
if slot_start = '1' then
if ssync = '1' then
tx_reg <= CreateTag(slot_valid) & "0000";
else
if slotcnt /= 0 then
tx_reg <= data_array(slotcnt);
if slotcnt = 12 then
last_slot <= '1';
end if;
end if;
end if;
else
tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0';
end if;
end if;
end process;
------------------------------------------------------------------
proc_ac_sync_out:
process (ac_reset, ac_bit_clk, ssync, tx_reg)
begin
if ac_reset = '1' then
ac_ssync <= '0';
ac_sdata_out <= '0';
elsif rising_edge(ac_bit_clk) then
ac_ssync <= ssync;
ac_sdata_out <= tx_reg(tx_reg'left);
end if;
end process;
------------------------------------------------------------------
singleshot_inst1: singleshot
GENERIC MAP (
mode => 0)
PORT MAP(
rst => rst,
clk => clk,
input => last_slot,
output => sync_tx
projects/ac97_Controller/src/cpu_embedded.vhd
+109
View File
@@ -0,0 +1,109 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity cpu_embedded is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
int_in : in STD_LOGIC;
int_ack : out STD_LOGIC;
xmem_we : out STD_LOGIC;
xmem_re : out STD_LOGIC;
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
io_sel : out STD_LOGIC
);
end cpu_embedded;
architecture rtl of cpu_embedded is
signal rom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0);
signal rom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
COMPONENT cpu
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
int_in : in STD_LOGIC;
int_ack : out STD_LOGIC;
xmem_wait : in STD_LOGIC;
xmem_we : out STD_LOGIC;
xmem_re : out STD_LOGIC;
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
io_sel : out STD_LOGIC
);
END COMPONENT;
COMPONENT irom
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in inst_addr_t;
dout : out inst_t
);
END COMPONENT;
begin
inst_cpu: cpu
PORT MAP(
rst => rst,
clk => clk,
ce => ce,
int_in => int_in,
int_ack => int_ack,
xmem_wait => '0',
xmem_we => xmem_we,
xmem_re => xmem_re,
instr_din => rom_data,
instr_addr => rom_addr,
xmem_din => xmem_din,
xmem_dout => xmem_dout,
xmem_addr => xmem_addr,
io_sel => io_sel
);
inst_irom: irom
PORT MAP(
clk => clk,
ce => ce,
addr => rom_addr,
dout => rom_data
);
end rtl;
projects/ac97_Controller/src/syn_fir_bandpass.vhd
+190
View File
@@ -0,0 +1,190 @@
-------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.fixed_pkg.all;
use work.filter_pkg.all;
use work.fir_stage_pkg.all;
use work.fir_iterative_pkg.all;
ENTITY syn_fir_bandpass IS
Generic (
ntaps : integer := 251;
nbits_in : integer := 18;
nbits_in_frac : integer := 18;
nbits_stages : integer := 18;
nbits_stages_frac : integer := 18;
nbits_out : integer := 18;
nbits_out_frac : integer := 18;
fir_mode : fir_iterative_mode_t := normal;
rounding : boolean := false;
saturating : boolean := false
);
PORT(
rst : in std_logic;
clk : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(nbits_in-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(nbits_out-1 downto 0);
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(nbits_in-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(nbits_out-1 downto 0)
);
END syn_fir_bandpass;
ARCHITECTURE behavior OF syn_fir_bandpass IS
-- Lowpass parameter
constant fa : real := 48000.0;
constant fm : real := 12000.0;
constant bw2 : real := 20000.0;
constant amp : real := 1.0;
constant omega_m : real := fm/fa;
constant omega_bw2 : real := bw2/fa;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fir_iterative
GENERIC
(
ntaps : integer;
nbits_in : integer;
nbits_in_frac : integer;
nbits_stages : integer;
nbits_stages_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
fir_mode : fir_iterative_mode_t;
rounding : boolean;
saturating : boolean
);
PORT
(
srst : in std_logic;
clk : in std_logic;
h_din : in sfixed;
h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
ready : out std_logic;
x_valid : in std_logic;
x_din : in sfixed;
y_dout_valid : out std_logic;
y_dout : out sfixed
);
END COMPONENT;
type h_mem_t is array (0 to ntaps-1) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
variable res : h_mem_t;
begin
for i in 0 to ntaps-1 loop
res(i) := to_sfixed(coef_real(i), proto, fixed_round, fixed_saturate);
end loop;
return res;
end to_h_mem;
constant ntaps_needed : integer := ntaps_addr(ntaps, fir_mode);
--Outputs
SIGNAL h_i, h_q : sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
SIGNAL x_i, x_q : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
SIGNAL y_i, y_q : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
SIGNAL h_addr_i, h_addr_q : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
-- ROM
CONSTANT coeffs : real_array_t(0 to ntaps_needed-1) := FilterCoef_Bandpass(ntaps, omega_bw2, omega_m, amp)(0 to ntaps_needed-1);
-- CONSTANT coeffs : real_array_t(0 to ntaps_needed-1) := FilterCoef_Delta(ntaps, 0, 0.999)(0 to ntaps_needed-1);
CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps_needed, h_i);
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_fir_iterative_i: fir_iterative
GENERIC MAP
(
ntaps => ntaps,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
fir_mode => fir_mode,
rounding => rounding,
saturating => saturating
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => h_i,
h_addr_out => h_addr_i,
ready => ready_i,
x_valid => x_valid_i,
x_din => x_i,
y_dout_valid => y_valid_i,
y_dout => y_i
);
inst_fir_iterative_q: fir_iterative
GENERIC MAP
(
ntaps => ntaps,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
fir_mode => fir_mode,
rounding => rounding,
saturating => saturating
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => h_q,
h_addr_out => h_addr_q,
ready => ready_q,
x_valid => x_valid_q,
x_din => x_q,
y_dout_valid => y_valid_Q,
y_dout => y_q
);
x_i <= sfixed(x_din_i);
y_dout_i <= signed(y_i);
x_q <= sfixed(x_din_q);
y_dout_q <= signed(y_q);
process(clk)
begin
if rising_edge(clk) then
h_i <= h_mem(to_integer(h_addr_i));
h_q <= h_mem(to_integer(h_addr_q));
end if;
end process;
END;
projects/ac97_Controller/src/syn_fir_lowpass.vhd
+191
View File
@@ -0,0 +1,191 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_stage_pkg.all;
use work.fir_iterative_pkg.all;
ENTITY syn_fir_lowpass IS
Generic (
ntaps : integer := 63;
nbits_in : integer := 24;
nbits_in_frac : integer := 22;
nbits_stages : integer := 36;
nbits_stages_frac : integer := 34;
nbits_out : integer := 32;
nbits_out_frac : integer := 31;
fir_mode : fir_iterative_mode_t := symmetric;
rounding : boolean := false;
saturating : boolean := false
);
PORT(
rst : in std_logic;
clk : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(nbits_in-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(nbits_out-1 downto 0);
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(nbits_in-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(nbits_out-1 downto 0)
);
END syn_fir_lowpass;
ARCHITECTURE behavior OF syn_fir_lowpass IS
-- Lowpass parameter
constant fa : real := 48000.0;
constant f : real := 10000.0;
constant amp : real := 1.0;
constant omega : real := f/fa;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fir_iterative
GENERIC
(
ntaps : integer;
nbits_in : integer;
nbits_in_frac : integer;
nbits_stages : integer;
nbits_stages_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
fir_mode : fir_iterative_mode_t;
rounding : boolean;
saturating : boolean
);
PORT
(
srst : in std_logic;
clk : in std_logic;
h_din : in sfixed;
h_addr_out : out natural;
ready : out std_logic;
x_valid : in std_logic;
x_din : in sfixed;
y_dout_valid : out std_logic;
y_dout : out sfixed
);
END COMPONENT;
type h_mem_t is array (0 to ntaps-1) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
variable res : h_mem_t;
begin
for i in 0 to ntaps-1 loop
res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
end loop;
return res;
end to_h_mem;
constant ntaps_needed : integer := ntaps_addr(ntaps, fir_mode);
--Outputs
SIGNAL h_i, h_q : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
SIGNAL x_i, x_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL y_i, y_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL h_addr_i, h_addr_q : natural;
-- ROM
CONSTANT coeffs : real_array_t(0 to ntaps_needed-1) := FilterCoef_Lowpass(ntaps, omega, amp)(0 to ntaps_needed-1);
CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps_needed, h_i);
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_fir_iterative_i: fir_iterative
GENERIC MAP
(
ntaps => ntaps,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
fir_mode => fir_mode,
rounding => rounding,
saturating => saturating
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => h_i,
h_addr_out => h_addr_i,
ready => ready_i,
x_valid => x_valid_i,
x_din => x_i,
y_dout_valid => y_valid_i,
y_dout => y_i
);
inst_fir_iterative_q: fir_iterative
GENERIC MAP
(
ntaps => ntaps,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
fir_mode => fir_mode,
rounding => rounding,
saturating => saturating
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => h_q,
h_addr_out => h_addr_q,
ready => ready_q,
x_valid => x_valid_q,
x_din => x_q,
y_dout_valid => y_valid_Q,
y_dout => y_q
);
x_i <= sfixed(x_din_i);
y_dout_i <= signed(y_i);
x_q <= sfixed(x_din_q);
y_dout_q <= signed(y_q);
process(clk)
begin
if rising_edge(clk) then
h_i <= h_mem(h_addr_i);
h_q <= h_mem(h_addr_q);
end if;
end process;
END;
projects/ac97_Controller/src/syn_fir_lowpass.vhd.bak
+191
View File
@@ -0,0 +1,191 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_stage_pkg.all;
use work.fir_iterative_pkg.all;
ENTITY syn_fir_lowpass IS
Generic (
ntaps : integer := 63;
nbits_in : integer := 24;
nbits_in_frac : integer := 22;
nbits_stages : integer := 36;
nbits_stages_frac : integer := 34;
nbits_out : integer := 32;
nbits_out_frac : integer := 31;
fir_mode : fir_iterative_mode_t := symmetric;
rounding : boolean := false;
saturating : boolean := false
);
PORT(
rst : in std_logic;
clk : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(nbits_in-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(nbits_out-1 downto 0);
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(nbits_in-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(nbits_out-1 downto 0)
);
END syn_fir_lowpass;
ARCHITECTURE behavior OF syn_fir_lowpass IS
-- Lowpass parameter
constant fa : real := 48000.0;
constant f : real := 10000.0;
constant amp : real := 1.0;
constant omega : real := f/fa;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fir_iterative
GENERIC
(
ntaps : integer;
nbits_in : integer;
nbits_in_frac : integer;
nbits_stages : integer;
nbits_stages_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
fir_mode : fir_iterative_mode_t;
rounding : boolean;
saturating : boolean
);
PORT
(
srst : in std_logic;
clk : in std_logic;
h_din : in sfixed;
h_addr_out : out integer;
ready : out std_logic;
x_valid : in std_logic;
x_din : in sfixed;
y_dout_valid : out std_logic;
y_dout : out sfixed
);
END COMPONENT;
type h_mem_t is array (0 to ntaps-1) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
variable res : h_mem_t;
begin
for i in 0 to ntaps-1 loop
res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
end loop;
return res;
end to_h_mem;
constant ntaps_needed : integer := ntaps_addr(ntaps, fir_mode);
--Outputs
SIGNAL h_i, h_q : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
SIGNAL x_i, x_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL y_i, y_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL h_addr_i, h_addr_q : integer;
-- ROM
CONSTANT coeffs : real_array_t(0 to ntaps_needed-1) := FilterCoef_Lowpass(ntaps, omega, amp)(0 to ntaps_needed-1);
CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps_needed, h_i);
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_fir_iterative_i: fir_iterative
GENERIC MAP
(
ntaps => ntaps,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
fir_mode => fir_mode,
rounding => rounding,
saturating => saturating
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => h_i,
h_addr_out => h_addr_i,
ready => ready_i,
x_valid => x_valid_i,
x_din => x_i,
y_dout_valid => y_valid_i,
y_dout => y_i
);
inst_fir_iterative_q: fir_iterative
GENERIC MAP
(
ntaps => ntaps,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
fir_mode => fir_mode,
rounding => rounding,
saturating => saturating
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => h_q,
h_addr_out => h_addr_q,
ready => ready_q,
x_valid => x_valid_q,
x_din => x_q,
y_dout_valid => y_valid_Q,
y_dout => y_q
);
x_i <= sfixed(x_din_i);
y_dout_i <= signed(y_i);
x_q <= sfixed(x_din_q);
y_dout_q <= signed(y_q);
process(clk)
begin
if rising_edge(clk) then
h_i <= h_mem(to_integer(h_addr_i));
h_q <= h_mem(to_integer(h_addr_q));
end if;
end process;
END;
projects/ac97_Controller/src/syn_fir_lowpass_sp.vhd
+141
View File
@@ -0,0 +1,141 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_pkg.all;
ENTITY syn_fir_lowpass IS
Generic
(
ntaps_per_stage : integer := 32;
nstages : integer := 2;
nbits_in : integer := 16;
nbits_in_frac : integer := 14;
nbits_stages : integer := 32;
nbits_stages_frac : integer := 30;
nbits_out : integer := 32;
nbits_out_frac : integer := 30;
fir_npipe_regs : integer := 7
);
PORT(
rst : in std_logic;
clk : in std_logic;
h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
h_we : in std_logic;
h_din : in signed(nbits_stages-1 downto 0);
start_i : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(nbits_in-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(nbits_out-1 downto 0);
start_q : in std_logic;
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(nbits_in-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(nbits_out-1 downto 0)
);
END syn_fir_lowpass;
ARCHITECTURE behavior OF syn_fir_lowpass IS
-- Lowpass parameter
--Outputs
SIGNAL h_i, h_q : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
SIGNAL x_i, x_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL y_i, y_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_fir_semi_parallel_i : entity work.fir_semi_parallel
GENERIC MAP
(
ntaps_per_stage => ntaps_per_stage,
nstages => nstages,
pipe_latency => fir_npipe_regs,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac
)
PORT MAP
(
rst => rst,
clk => clk,
h_addr => h_addr,
h_we => h_we,
h_in => h_in,
din_vld => x_valid_i,
din => x_i,
dout_vld => y_valid_i,
start => start_i,
rdy => ready_i,
dout => y_i
);
inst_fir_semi_parallel_q : entity work.fir_semi_parallel
GENERIC MAP
(
ntaps_per_stage => ntaps_per_stage,
nstages => nstages,
pipe_latency => fir_npipe_regs,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac
)
PORT MAP
(
rst => rst,
clk => clk,
h_addr => h_addr,
h_we => h_we,
h_in => h_in,
din_vld => x_valid_q,
din => x_q,
dout_vld => y_valid_q,
start => start_q,
rdy => ready_q,
dout => y_q
);
h_in <= sfixed(h_din);
x_i <= sfixed(x_din_i);
y_dout_i <= signed(y_i);
x_q <= sfixed(x_din_q);
y_dout_q <= signed(y_q);
END;
projects/ac97_Controller/src/syn_fir_lowpass_sp.vhd.bak
+141
View File
@@ -0,0 +1,141 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_pkg.all;
ENTITY syn_fir_lowpass IS
Generic
(
ntaps_per_stage : integer := 32;
nstages : integer := 2;
nbits_in : integer := 16;
nbits_in_frac : integer := 14;
nbits_stages : integer := 32;
nbits_stages_frac : integer := 30;
nbits_out : integer := 32;
nbits_out_frac : integer := 30;
fir_npipe_regs : integer := 6
);
PORT(
rst : in std_logic;
clk : in std_logic;
h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
h_we : in std_logic;
h_din : in signed(nbits_stages-1 downto 0);
start_i : in std_logic;
ready_i : out std_logic;
x_valid_i : in std_logic;
x_din_i : in signed(nbits_in-1 downto 0);
y_valid_i : out std_logic;
y_dout_i : out signed(nbits_out-1 downto 0);
start_q : in std_logic;
ready_q : out std_logic;
x_valid_q : in std_logic;
x_din_q : in signed(nbits_in-1 downto 0);
y_valid_q : out std_logic;
y_dout_q : out signed(nbits_out-1 downto 0)
);
END syn_fir_lowpass;
ARCHITECTURE behavior OF syn_fir_lowpass IS
-- Lowpass parameter
--Outputs
SIGNAL h_i, h_q : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
SIGNAL x_i, x_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL y_i, y_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_fir_semi_parallel_i : entity work.fir_semi_parallel
GENERIC MAP
(
ntaps_per_stage => ntaps_per_stage,
nstages => nstages,
pipe_latency => fir_npipe_regs,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac
)
PORT MAP
(
rst => rst,
clk => clk,
h_addr => h_addr,
h_we => h_we,
h_in => h_in,
din_vld => x_valid_i,
din => x_i,
dout_vld => y_valid_i,
start => start_i,
rdy => ready_i,
dout => y_i
);
inst_fir_semi_parallel_q : entity work.fir_semi_parallel
GENERIC MAP
(
ntaps_per_stage => ntaps_per_stage,
nstages => nstages,
pipe_latency => fir_npipe_regs,
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_stages => nbits_stages,
nbits_stages_frac => nbits_stages_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac
)
PORT MAP
(
rst => rst,
clk => clk,
h_addr => h_addr,
h_we => h_we,
h_in => h_in,
din_vld => x_valid_q,
din => x_q,
dout_vld => y_valid_q,
start => start_q,
rdy => ready_q,
dout => y_q
);
h_in <= sfixed(h_din);
x_i <= sfixed(x_din_i);
y_dout_i <= signed(y_i);
x_q <= sfixed(x_din_q);
y_dout_q <= signed(y_q);
END;
projects/ac97_Controller/src/syn_nco.vhd
+120
View File
@@ -0,0 +1,120 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.fixed_pkg.all;
use work.nco_pkg.all;
ENTITY syn_nco IS
Generic (
nbits_wave : integer := 18;
nbits_phase : integer := 16;
nbits_lut_depth : integer := 12;
nbits_dither : integer := 4;
nbits_lfsr : integer := 12;
q_phase : phase_relation_t := phase_270deg;
has_pipe_reg : boolean := true;
has_out_reg : boolean := true
);
PORT(
rst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out signed(nbits_wave-1 downto 0);
wave_out_q : out signed(nbits_wave-1 downto 0);
out_valid : out std_logic
);
END syn_nco;
ARCHITECTURE behavior OF syn_nco IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nco
GENERIC (
nbits_wave : integer;
nbits_phase : integer;
nbits_lut_depth : integer;
nbits_dither : integer;
nbits_lfsr : integer;
q_phase : phase_relation_t;
has_pipe_reg : boolean;
has_out_reg : boolean
);
PORT(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic
);
END COMPONENT;
--Constants
constant nbits_wave_frac : integer := nbits_wave;
--Outputs
SIGNAL wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
SIGNAL wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_nco: nco
GENERIC MAP (
nbits_wave => nbits_wave,
nbits_phase => nbits_phase,
nbits_lut_depth => nbits_lut_depth,
nbits_dither => nbits_dither,
nbits_lfsr => nbits_lfsr,
q_phase => q_phase,
has_pipe_reg => has_pipe_reg,
has_out_reg => has_out_reg
)
PORT MAP(
srst => rst,
clk => clk,
pacc_clr => pacc_clr,
pacc_inc => pacc_inc,
freq_in => freq_in,
freq_load => freq_load,
phase_in => phase_in,
phase_load => phase_load,
phase_out => phase_out,
wave_out_i => wave_i,
wave_out_q => wave_q,
out_valid => out_valid
);
wave_out_i <= signed(wave_i);
wave_out_q <= signed(wave_q);
END;
projects/ac97_Controller/src/tb_ac97_test.vhd
+144
View File
@@ -0,0 +1,144 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:39:41 06/16/2007
-- Design Name: ac97_test
-- Module Name: W:/vhdl/projects/ac97_Controller/src/tb_ac97_test.vhd
-- Project Name: eval_ac
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac97_test
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac97_test IS
END tb_ac97_test;
ARCHITECTURE behavior OF tb_ac97_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac97_test
PORT(
sys_rst_n_in : IN std_logic;
sys_clk_in : IN std_logic;
ac97_bit_clk : IN std_logic;
ac97_sdata_in : IN std_logic;
ac97_reset_n : OUT std_logic;
ac97_sdata_out : OUT std_logic;
ac97_sync : OUT std_logic;
sys_lcd_d : inout std_logic_vector(3 downto 0);
sys_lcd_e : out std_logic;
sys_lcd_rs : out std_logic;
sys_lcd_rw : out std_logic;
sys_rx : in std_logic;
sys_tx : out std_logic;
sys_btn : in STD_LOGIC_VECTOR(4 downto 0);
sys_dip : in STD_LOGIC_VECTOR(7 downto 0);
sys_led : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
CONSTANT CLK_PERIOD : time := 10 ns;
-- CONSTANT BIT_CLK_PERIOD : time := 100 ns;
CONSTANT BIT_CLK_PERIOD : time := 81.38020833333333 ns;
--Inputs
SIGNAL sys_rst_n_in : std_logic := '0';
SIGNAL sys_clk_in : std_logic := '0';
SIGNAL ac97_bit_clk : std_logic := '1';
SIGNAL ac97_sdata_in : std_logic := '0';
SIGNAL sys_rx : std_logic := '0';
SIGNAL sys_btn : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
SIGNAL sys_dip : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
SIGNAL sys_lcd_d : std_logic_vector(3 downto 0) := (others => 'Z');
--Outputs
SIGNAL ac97_reset_n : std_logic;
SIGNAL ac97_sdata_out : std_logic;
SIGNAL ac97_sync : std_logic;
SIGNAL sys_tx : std_logic;
SIGNAL sys_lcd_e : std_logic;
SIGNAL sys_lcd_rs : std_logic;
SIGNAL sys_lcd_rw : std_logic;
SIGNAL sys_led : std_logic_vector(8 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac97_test PORT MAP(
sys_rst_n_in => sys_rst_n_in,
sys_clk_in => sys_clk_in,
ac97_bit_clk => ac97_bit_clk,
ac97_sdata_in => ac97_sdata_in,
ac97_reset_n => ac97_reset_n,
ac97_sdata_out => ac97_sdata_out,
ac97_sync => ac97_sync,
sys_btn => sys_btn,
sys_dip => sys_dip,
sys_rx => sys_rx,
sys_tx => sys_tx,
sys_lcd_d => sys_lcd_d,
sys_lcd_e => sys_lcd_e,
sys_lcd_rs => sys_lcd_rs,
sys_lcd_rw => sys_lcd_rw,
sys_led => sys_led
);
clk_gen : PROCESS
begin
wait for CLK_PERIOD/2;
sys_clk_in <= not sys_clk_in;
end process;
bit_clk_gen : PROCESS
begin
if (ac97_reset_n = '0') then
ac97_bit_clk <= '0';
wait until ac97_reset_n = '1';
wait for 373.56 ns;
end if;
wait for BIT_CLK_PERIOD/2;
ac97_bit_clk <= not ac97_bit_clk;
end process;
tb : PROCESS
BEGIN
wait for 8 * CLK_PERIOD;
sys_rst_n_in <= '1';
wait for 1234 * BIT_CLK_PERIOD;
for i in 0 to 1000 loop
wait until rising_edge(ac97_bit_clk) and ac97_sync = '1';
ac97_sdata_in <= '1';
wait until rising_edge(ac97_bit_clk);
ac97_sdata_in <= '1';
end loop;
wait; -- will wait forever
END PROCESS;
END;
projects/ac97_Controller/src/tb_ac_in.vhd
+203
View File
@@ -0,0 +1,203 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac_in IS
END tb_ac_in;
ARCHITECTURE behavior OF tb_ac_in IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac_in
Port (
rst : in std_logic;
clk : in std_logic;
sync_frame : out std_logic;
sync_status : out std_logic;
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
pcm_out_addr : in unsigned (3 downto 0);
pcm_out_data : out unsigned (19 downto 0);
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_in : in std_logic;
ac_ssync : in std_logic
);
END COMPONENT;
COMPONENT ac_out
PORT(
rst : in std_logic;
clk : in std_logic;
sync_tx : out std_logic;
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
pcm_in_addr : in unsigned(3 downto 0);
pcm_in_data : in unsigned(19 downto 0);
pcm_in_we : in std_logic;
ac_bit_clk : in std_logic;
ac_reset : in std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
constant SYS_CLK_PERIOD : time := 10 ns;
constant BIT_CLK_PERIOD : time := 81.38 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL cmd_we : std_logic := '0';
SIGNAL pcm_in_we : std_logic := '0';
SIGNAL ac_bit_clk : std_logic := '0';
SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL pcm_in_addr : unsigned(3 downto 0) := "0011";
SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL ac_sdata_in : std_logic;
SIGNAL pcm_out_addr : unsigned(3 downto 0) := "0101";
SIGNAL ac_reset : std_logic := '1';
--Outputs
SIGNAL sync_frame : std_logic;
SIGNAL sync_status : std_logic;
SIGNAL sync_tx : std_logic;
SIGNAL ac_sdata_out : std_logic;
SIGNAL ac_ssync : std_logic;
SIGNAL stat_addr : unsigned(19 downto 0);
SIGNAL stat_data : unsigned(19 downto 0);
SIGNAL stat_valid : std_logic;
SIGNAL pcm_out_data : unsigned(19 downto 0);
SIGNAL pcm_out_valid : std_logic;
SIGNAL pcm_out_avail : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac_in PORT MAP(
rst => rst,
clk => clk,
sync_frame => sync_frame,
sync_status => sync_status,
stat_addr => stat_addr,
stat_data => stat_data,
pcm_out_addr => pcm_out_addr,
pcm_out_data => pcm_out_data,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_in => ac_sdata_in,
ac_ssync => ac_ssync
);
inst_ac_out: ac_out PORT MAP(
rst => rst,
clk => clk,
sync_tx => sync_tx,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
pcm_in_addr => pcm_in_addr,
pcm_in_data => pcm_in_data,
pcm_in_we => pcm_in_we,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_out => ac_sdata_out,
ac_ssync => ac_ssync
);
ac_sdata_in <= ac_sdata_out;
sys_clk_gen :
PROCESS
BEGIN
wait for SYS_CLK_PERIOD;
clk <= not clk;
END PROCESS;
bit_clk_gen :
PROCESS
BEGIN
wait for BIT_CLK_PERIOD;
ac_bit_clk <= not ac_bit_clk;
END PROCESS;
tb_out : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100*SYS_CLK_PERIOD;
rst <= '0';
wait for 100*SYS_CLK_PERIOD;
ac_reset <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
cmd_data <= X"12340";
cmd_addr <= X"8B930";
wait until rising_edge(clk);
cmd_we <= '1';
wait until rising_edge(clk);
cmd_we <= '0';
for k in 1 to 10 loop
pcm_in_we <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
for i in 3 to 12 loop
pcm_in_addr <= to_unsigned(i, 4);
pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
pcm_in_we <= '1';
wait until rising_edge(clk);
end loop;
end loop;
pcm_in_we <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
tb_in : PROCESS(clk, pcm_out_addr, sync_status)
BEGIN
if rising_edge(clk) then
if sync_status = '1' then
pcm_out_addr <= "0011";
elsif pcm_out_addr /= "1100" then
pcm_out_addr <= pcm_out_addr + 1;
end if;
end if;
END PROCESS;
END;
projects/ac97_Controller/src/tb_ac_io.vhd
+186
View File
@@ -0,0 +1,186 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac_io IS
END tb_ac_io;
ARCHITECTURE behavior OF tb_ac_io IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac_io
Port (
rst : in std_logic;
clk : in std_logic;
ready : out std_logic;
sync_strobe : out unsigned(0 to 2);
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
rx_pcm_addr : in unsigned (3 downto 0);
rx_pcm_data : out unsigned (19 downto 0);
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
tx_pcm_addr : in unsigned(3 downto 0);
tx_pcm_data : in unsigned(19 downto 0);
tx_pcm_we : in std_logic;
ac_sdata_in : in std_logic;
ac_bit_clk : in std_logic;
ac_reset_n : out std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
constant SYS_CLK_PERIOD : time := 10 ns;
CONSTANT BIT_CLK_PERIOD : time := 100 ns;
-- constant BIT_CLK_PERIOD : time := 81.38 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL acio_ready : std_logic;
SIGNAL cmd_we : std_logic := '0';
SIGNAL tx_pcm_we : std_logic := '0';
SIGNAL ac_bit_clk : std_logic := '0';
SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL tx_pcm_addr : unsigned(3 downto 0) := "0011";
SIGNAL tx_pcm_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL ac_sdata_in : std_logic;
SIGNAL rx_pcm_addr : unsigned(3 downto 0) := "0101";
--Outputs
SIGNAL slot_valid : unsigned(0 to 12);
SIGNAL sync_strobe : unsigned(0 to 2);
SIGNAL ac_reset_n : std_logic;
SIGNAL ac_sdata_out : std_logic;
SIGNAL ac_ssync : std_logic;
SIGNAL stat_addr : unsigned(19 downto 0);
SIGNAL stat_data : unsigned(19 downto 0);
SIGNAL rx_pcm_data : unsigned(19 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac_io PORT MAP(
rst => rst,
clk => clk,
ready => acio_ready,
sync_strobe => sync_strobe,
slot_valid => slot_valid,
stat_addr => stat_addr,
stat_data => stat_data,
rx_pcm_addr => rx_pcm_addr,
rx_pcm_data => rx_pcm_data,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
tx_pcm_addr => tx_pcm_addr,
tx_pcm_data => tx_pcm_data,
tx_pcm_we => tx_pcm_we,
ac_sdata_in => ac_sdata_in,
ac_bit_clk => ac_bit_clk,
ac_reset_n => ac_reset_n,
ac_sdata_out => ac_sdata_out,
ac_ssync => ac_ssync
);
ac_sdata_in <= ac_sdata_out;
sys_clk_gen :
PROCESS
BEGIN
wait for SYS_CLK_PERIOD;
clk <= not clk;
END PROCESS;
bit_clk_gen : PROCESS
begin
if (ac_reset_n = '0') then
ac_bit_clk <= '0';
wait until ac_reset_n = '1';
wait for 150 us;
end if;
wait for BIT_CLK_PERIOD/2;
ac_bit_clk <= not ac_bit_clk;
END PROCESS;
tb_out : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100*SYS_CLK_PERIOD;
rst <= '0';
wait until (ac_reset_n = '1');
wait until rising_edge(clk) and sync_strobe(2) = '1';
wait for 100*SYS_CLK_PERIOD;
cmd_data <= X"12340";
cmd_addr <= X"8B930";
wait until rising_edge(clk);
cmd_we <= '1';
wait until rising_edge(clk);
cmd_we <= '0';
for k in 1 to 10 loop
tx_pcm_we <= '0';
wait until rising_edge(clk) and sync_strobe(2) = '1';
wait for 10*BIT_CLK_PERIOD;
for i in 3 to 12 loop
tx_pcm_addr <= to_unsigned(i, 4);
tx_pcm_data <= to_unsigned(2048*k + integer(i), 20);
tx_pcm_we <= '1';
wait until rising_edge(clk);
end loop;
end loop;
tx_pcm_we <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe)
BEGIN
if rising_edge(clk) then
if sync_strobe(1) = '1' then
rx_pcm_addr <= "0011";
elsif rx_pcm_addr /= "1100" then
rx_pcm_addr <= rx_pcm_addr + 1;
end if;
end if;
END PROCESS;
END;
projects/ac97_Controller/src/tb_ac_out.vhd
+149
View File
@@ -0,0 +1,149 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac_out IS
END tb_ac_out;
ARCHITECTURE behavior OF tb_ac_out IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac_out
PORT(
rst : IN std_logic;
clk : IN std_logic;
sync_tx : OUT std_logic;
cmd_addr : IN unsigned(19 downto 0);
cmd_data : IN unsigned(19 downto 0);
cmd_we : IN std_logic;
pcm_in_addr : IN unsigned(3 downto 0);
pcm_in_data : IN unsigned(19 downto 0);
pcm_in_we : IN std_logic;
ac_bit_clk : IN std_logic;
ac_reset : in std_logic;
ac_sdata_out : OUT std_logic;
ac_ssync : OUT std_logic
);
END COMPONENT;
constant SYS_CLK_PERIOD : time := 10 ns;
constant BIT_CLK_PERIOD : time := 81.38 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL ce : std_logic := '0';
SIGNAL cmd_we : std_logic := '0';
SIGNAL pcm_in_we : std_logic := '0';
SIGNAL ac_bit_clk : std_logic := '0';
SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL pcm_in_addr : unsigned(3 downto 0) := (others=>'0');
SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0');
--Outputs
SIGNAL sync_tx : std_logic;
SIGNAL ac_reset : std_logic;
SIGNAL ac_sdata_out : std_logic;
SIGNAL ac_ssync : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac_out PORT MAP(
rst => rst,
clk => clk,
sync_tx => sync_tx,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
pcm_in_addr => pcm_in_addr,
pcm_in_data => pcm_in_data,
pcm_in_we => pcm_in_we,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_out => ac_sdata_out,
ac_ssync => ac_ssync
);
sys_clk_gen :
PROCESS
BEGIN
wait for SYS_CLK_PERIOD;
clk <= not clk;
END PROCESS;
bit_clk_gen :
PROCESS
BEGIN
wait for BIT_CLK_PERIOD;
ac_bit_clk <= not ac_bit_clk;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100*SYS_CLK_PERIOD;
rst <= '0';
wait for 100*SYS_CLK_PERIOD;
ac_reset <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
cmd_data <= X"aaaa0";
cmd_addr <= X"1DFC0";
wait until rising_edge(clk);
cmd_we <= '1';
wait until rising_edge(clk);
cmd_we <= '0';
for k in 1 to 10 loop
pcm_in_we <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
for i in 3 to 12 loop
pcm_in_addr <= to_unsigned(i, 4);
pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
pcm_in_we <= '1';
wait until rising_edge(clk);
end loop;
end loop;
pcm_in_we <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
projects/ac97_Controller/src/test_irom.vhdl
+566
View File
@@ -0,0 +1,566 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.cpu_pkg.all;
-- JASM_ROM_INSERT_HERE
ENTITY irom IS
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in inst_addr_t;
dout : out inst_t
);
END irom;
ARCHITECTURE test OF irom IS
type imem_rom_t is array (0 to 503) of inst_t;
-- Assembled from test.jsm
constant imem_rom : imem_rom_t :=
(
"110000" & X"002", -- 0x000: JMP 0x002
"110000" & X"0B5", -- 0x001: JMP 0x0B5
"000011" & X"000", -- 0x002: MOV R00, 0x00
"000011" & X"001", -- 0x003: MOV R01, 0x00
"000011" & X"002", -- 0x004: MOV R02, 0x00
"000011" & X"003", -- 0x005: MOV R03, 0x00
"100100" & X"000", -- 0x006: XOUT (0x00), R00
"001101" & X"000", -- 0x007: MOVC (0x00), R00
"001101" & X"100", -- 0x008: MOVC (0x10), R00
"001101" & X"110", -- 0x009: MOVC (0x11), R00
"001101" & X"080", -- 0x00A: MOVC (0x08), R00
"001101" & X"090", -- 0x00B: MOVC (0x09), R00
"000011" & X"800", -- 0x00C: MOV R00, 0x80
"000011" & X"001", -- 0x00D: MOV R01, 0x00
"001101" & X"0E0", -- 0x00E: MOVC (0x0E), R00
"001101" & X"0F1", -- 0x00F: MOVC (0x0F), R01
"111011" & X"17A", -- 0x010: CALL 0x17A
"111011" & X"0F3", -- 0x011: CALL 0x0F3
"000011" & X"010", -- 0x012: MOV R00, 0x01
"111011" & X"197", -- 0x013: CALL 0x197
"000011" & X"001", -- 0x014: MOV R01, 0x00
"111011" & X"19C", -- 0x015: CALL 0x19C
"101000" & X"A00", -- 0x016: XIN R00, (0xA0)
"011001" & X"010", -- 0x017: AND R00, 0x01
"110001" & X"016", -- 0x018: JZ 0x016
"101000" & X"A00", -- 0x019: XIN R00, (0xA0)
"011001" & X"080", -- 0x01A: AND R00, 0x08
"110001" & X"019", -- 0x01B: JZ 0x019
"111011" & X"145", -- 0x01C: CALL 0x145
"000011" & X"000", -- 0x01D: MOV R00, 0x00
"000011" & X"801", -- 0x01E: MOV R01, 0x80
"000011" & X"002", -- 0x01F: MOV R02, 0x00
"000011" & X"003", -- 0x020: MOV R03, 0x00
"111011" & X"0D4", -- 0x021: CALL 0x0D4
"001101" & X"020", -- 0x022: MOVC (0x02), R00
"001101" & X"031", -- 0x023: MOVC (0x03), R01
"001101" & X"042", -- 0x024: MOVC (0x04), R02
"001101" & X"053", -- 0x025: MOVC (0x05), R03
"000011" & X"000", -- 0x026: MOV R00, 0x00
"000011" & X"A61", -- 0x027: MOV R01, 0xA6
"000011" & X"002", -- 0x028: MOV R02, 0x00
"000011" & X"003", -- 0x029: MOV R03, 0x00
"111011" & X"0D4", -- 0x02A: CALL 0x0D4
"011001" & X"0F2", -- 0x02B: AND R02, 0x0F
"001111" & X"0F2", -- 0x02C: CMP R02, 0x0F
"111010" & X"026", -- 0x02D: JNE 0x026
"000011" & X"09F", -- 0x02E: MOV R15, 0x09
"000011" & X"107", -- 0x02F: MOV R07, 0x10
"000011" & X"228", -- 0x030: MOV R08, 0x22
"000100" & X"070", -- 0x031: MOVX R00, (R07)
"010001" & X"017", -- 0x032: INC R07
"000100" & X"071", -- 0x033: MOVX R01, (R07)
"010001" & X"017", -- 0x034: INC R07
"000100" & X"082", -- 0x035: MOVX R02, (R08)
"010001" & X"018", -- 0x036: INC R08
"000100" & X"083", -- 0x037: MOVX R03, (R08)
"010001" & X"018", -- 0x038: INC R08
"111011" & X"0D4", -- 0x039: CALL 0x0D4
"010101" & X"01F", -- 0x03A: DEC R15
"110010" & X"031", -- 0x03B: JNZ 0x031
"000011" & X"010", -- 0x03C: MOV R00, 0x01
"111011" & X"197", -- 0x03D: CALL 0x197
"000011" & X"410", -- 0x03E: MOV R00, 0x41
"111011" & X"1AE", -- 0x03F: CALL 0x1AE
"000011" & X"3A0", -- 0x040: MOV R00, 0x3A
"111011" & X"1AE", -- 0x041: CALL 0x1AE
"001010" & X"030", -- 0x042: MOVC R00, (0x03)
"111011" & X"0EE", -- 0x043: CALL 0x0EE
"001010" & X"020", -- 0x044: MOVC R00, (0x02)
"111011" & X"0EE", -- 0x045: CALL 0x0EE
"000011" & X"200", -- 0x046: MOV R00, 0x20
"111011" & X"1AE", -- 0x047: CALL 0x1AE
"000011" & X"440", -- 0x048: MOV R00, 0x44
"111011" & X"1AE", -- 0x049: CALL 0x1AE
"000011" & X"3A0", -- 0x04A: MOV R00, 0x3A
"111011" & X"1AE", -- 0x04B: CALL 0x1AE
"001010" & X"050", -- 0x04C: MOVC R00, (0x05)
"111011" & X"0EE", -- 0x04D: CALL 0x0EE
"001010" & X"040", -- 0x04E: MOVC R00, (0x04)
"111011" & X"0EE", -- 0x04F: CALL 0x0EE
"000011" & X"000", -- 0x050: MOV R00, 0x00
"100100" & X"010", -- 0x051: XOUT (0x01), R00
"000011" & X"400", -- 0x052: MOV R00, 0x40
"100100" & X"030", -- 0x053: XOUT (0x03), R00
"000011" & X"000", -- 0x054: MOV R00, 0x00
"100100" & X"020", -- 0x055: XOUT (0x02), R00
"000011" & X"FF0", -- 0x056: MOV R00, 0xFF
"100100" & X"0E0", -- 0x057: XOUT (0x0E), R00
"000011" & X"400", -- 0x058: MOV R00, 0x40
"100100" & X"0D0", -- 0x059: XOUT (0x0D), R00
"000011" & X"FF0", -- 0x05A: MOV R00, 0xFF
"100100" & X"100", -- 0x05B: XOUT (0x10), R00
"000011" & X"400", -- 0x05C: MOV R00, 0x40
"100100" & X"0F0", -- 0x05D: XOUT (0x0F), R00
"000011" & X"000", -- 0x05E: MOV R00, 0x00
"100100" & X"0A0", -- 0x05F: XOUT (0x0A), R00
"000011" & X"5C0", -- 0x060: MOV R00, 0x5C
"100100" & X"090", -- 0x061: XOUT (0x09), R00
"000011" & X"000", -- 0x062: MOV R00, 0x00
"100100" & X"0C0", -- 0x063: XOUT (0x0C), R00
"000011" & X"5C0", -- 0x064: MOV R00, 0x5C
"100100" & X"0B0", -- 0x065: XOUT (0x0B), R00
"101000" & X"000", -- 0x066: XIN R00, (0x00)
"011011" & X"010", -- 0x067: OR R00, 0x01
"100100" & X"000", -- 0x068: XOUT (0x00), R00
"000011" & X"070", -- 0x069: MOV R00, 0x07
"100110" & X"030", -- 0x06A: COUT (0x03), R00
"101000" & X"810", -- 0x06B: XIN R00, (0x81)
"001101" & X"010", -- 0x06C: MOVC (0x01), R00
"101000" & X"800", -- 0x06D: XIN R00, (0x80)
"001101" & X"000", -- 0x06E: MOVC (0x00), R00
"001010" & X"010", -- 0x06F: MOVC R00, (0x01)
"100100" & X"010", -- 0x070: XOUT (0x01), R00
"101000" & X"000", -- 0x071: XIN R00, (0x00)
"011001" & X"080", -- 0x072: AND R00, 0x08
"110010" & X"06B", -- 0x073: JNZ 0x06B
"000011" & X"C00", -- 0x074: MOV R00, 0xC0
"111011" & X"197", -- 0x075: CALL 0x197
"001010" & X"000", -- 0x076: MOVC R00, (0x00)
"011001" & X"100", -- 0x077: AND R00, 0x10
"110010" & X"082", -- 0x078: JNZ 0x082
"101000" & X"820", -- 0x079: XIN R00, (0x82)
"001101" & X"0A0", -- 0x07A: MOVC (0x0A), R00
"101000" & X"830", -- 0x07B: XIN R00, (0x83)
"001101" & X"0B0", -- 0x07C: MOVC (0x0B), R00
"101000" & X"840", -- 0x07D: XIN R00, (0x84)
"001101" & X"0C0", -- 0x07E: MOVC (0x0C), R00
"101000" & X"850", -- 0x07F: XIN R00, (0x85)
"001101" & X"0D0", -- 0x080: MOVC (0x0D), R00
"110000" & X"08A", -- 0x081: JMP 0x08A
"101000" & X"860", -- 0x082: XIN R00, (0x86)
"001101" & X"0A0", -- 0x083: MOVC (0x0A), R00
"101000" & X"870", -- 0x084: XIN R00, (0x87)
"001101" & X"0B0", -- 0x085: MOVC (0x0B), R00
"101000" & X"880", -- 0x086: XIN R00, (0x88)
"001101" & X"0C0", -- 0x087: MOVC (0x0C), R00
"101000" & X"890", -- 0x088: XIN R00, (0x89)
"001101" & X"0D0", -- 0x089: MOVC (0x0D), R00
"111011" & X"104", -- 0x08A: CALL 0x104
"000011" & X"4C0", -- 0x08B: MOV R00, 0x4C
"111011" & X"1AE", -- 0x08C: CALL 0x1AE
"000011" & X"3A0", -- 0x08D: MOV R00, 0x3A
"111011" & X"1AE", -- 0x08E: CALL 0x1AE
"001010" & X"0B0", -- 0x08F: MOVC R00, (0x0B)
"111011" & X"0EE", -- 0x090: CALL 0x0EE
"001010" & X"0A0", -- 0x091: MOVC R00, (0x0A)
"111011" & X"0EE", -- 0x092: CALL 0x0EE
"000011" & X"200", -- 0x093: MOV R00, 0x20
"111011" & X"1AE", -- 0x094: CALL 0x1AE
"000011" & X"520", -- 0x095: MOV R00, 0x52
"111011" & X"1AE", -- 0x096: CALL 0x1AE
"000011" & X"3A0", -- 0x097: MOV R00, 0x3A
"111011" & X"1AE", -- 0x098: CALL 0x1AE
"001010" & X"0D0", -- 0x099: MOVC R00, (0x0D)
"111011" & X"0EE", -- 0x09A: CALL 0x0EE
"001010" & X"0C0", -- 0x09B: MOVC R00, (0x0C)
"111011" & X"0EE", -- 0x09C: CALL 0x0EE
"001010" & X"000", -- 0x09D: MOVC R00, (0x00)
"011001" & X"010", -- 0x09E: AND R00, 0x01
"110001" & X"0A6", -- 0x09F: JZ 0x0A6
"101000" & X"020", -- 0x0A0: XIN R00, (0x02)
"101000" & X"031", -- 0x0A1: XIN R01, (0x03)
"010101" & X"640", -- 0x0A2: SUB R00, 0x64
"110100" & X"0AF", -- 0x0A3: JNC 0x0AF
"010101" & X"011", -- 0x0A4: DEC R01
"110000" & X"0AF", -- 0x0A5: JMP 0x0AF
"001010" & X"000", -- 0x0A6: MOVC R00, (0x00)
"011001" & X"040", -- 0x0A7: AND R00, 0x04
"110001" & X"0B4", -- 0x0A8: JZ 0x0B4
"101000" & X"020", -- 0x0A9: XIN R00, (0x02)
"101000" & X"031", -- 0x0AA: XIN R01, (0x03)
"010001" & X"640", -- 0x0AB: ADD R00, 0x64
"110100" & X"0AF", -- 0x0AC: JNC 0x0AF
"010001" & X"011", -- 0x0AD: INC R01
"110000" & X"0AF", -- 0x0AE: JMP 0x0AF
"100100" & X"031", -- 0x0AF: XOUT (0x03), R01
"100100" & X"020", -- 0x0B0: XOUT (0x02), R00
"101000" & X"000", -- 0x0B1: XIN R00, (0x00)
"011001" & X"080", -- 0x0B2: AND R00, 0x08
"110001" & X"0B1", -- 0x0B3: JZ 0x0B1
"110000" & X"06B", -- 0x0B4: JMP 0x06B
"111100" & X"000", -- 0x0B5: PUSH R00
"111100" & X"001", -- 0x0B6: PUSH R01
"001010" & X"100", -- 0x0B7: MOVC R00, (0x10)
"001010" & X"111", -- 0x0B8: MOVC R01, (0x11)
"010001" & X"010", -- 0x0B9: INC R00
"001111" & X"300", -- 0x0BA: CMP R00, 0x30
"110010" & X"0C6", -- 0x0BB: JNZ 0x0C6
"000011" & X"000", -- 0x0BC: MOV R00, 0x00
"111100" & X"000", -- 0x0BD: PUSH R00
"101000" & X"800", -- 0x0BE: XIN R00, (0x80)
"001101" & X"000", -- 0x0BF: MOVC (0x00), R00
"111101" & X"000", -- 0x0C0: POP R00
"010001" & X"011", -- 0x0C1: INC R01
"001111" & X"641", -- 0x0C2: CMP R01, 0x64
"110010" & X"0C6", -- 0x0C3: JNZ 0x0C6
"111011" & X"0CB", -- 0x0C4: CALL 0x0CB
"000011" & X"001", -- 0x0C5: MOV R01, 0x00
"001101" & X"100", -- 0x0C6: MOVC (0x10), R00
"001101" & X"111", -- 0x0C7: MOVC (0x11), R01
"111101" & X"001", -- 0x0C8: POP R01
"111101" & X"000", -- 0x0C9: POP R00
"111111" & X"000", -- 0x0CA: RETI
"101000" & X"000", -- 0x0CB: XIN R00, (0x00)
"000010" & X"001", -- 0x0CC: MOV R01, R00
"011001" & X"081", -- 0x0CD: AND R01, 0x08
"110010" & X"0D1", -- 0x0CE: JNZ 0x0D1
"011011" & X"080", -- 0x0CF: OR R00, 0x08
"110000" & X"0D2", -- 0x0D0: JMP 0x0D2
"011001" & X"F70", -- 0x0D1: AND R00, 0xF7
"100100" & X"000", -- 0x0D2: XOUT (0x00), R00
"111110" & X"000", -- 0x0D3: RET
"111011" & X"0E2", -- 0x0D4: CALL 0x0E2
"100100" & X"051", -- 0x0D5: XOUT (0x05), R01
"100100" & X"040", -- 0x0D6: XOUT (0x04), R00
"100100" & X"073", -- 0x0D7: XOUT (0x07), R03
"100100" & X"062", -- 0x0D8: XOUT (0x06), R02
"011001" & X"801", -- 0x0D9: AND R01, 0x80
"110010" & X"0DC", -- 0x0DA: JNZ 0x0DC
"111110" & X"000", -- 0x0DB: RET
"111011" & X"0E8", -- 0x0DC: CALL 0x0E8
"101000" & X"051", -- 0x0DD: XIN R01, (0x05)
"101000" & X"040", -- 0x0DE: XIN R00, (0x04)
"101000" & X"073", -- 0x0DF: XIN R03, (0x07)
"101000" & X"062", -- 0x0E0: XIN R02, (0x06)
"111110" & X"000", -- 0x0E1: RET
"111100" & X"000", -- 0x0E2: PUSH R00
"101000" & X"A00", -- 0x0E3: XIN R00, (0xA0)
"011001" & X"020", -- 0x0E4: AND R00, 0x02
"110001" & X"0E3", -- 0x0E5: JZ 0x0E3
"111101" & X"000", -- 0x0E6: POP R00
"111110" & X"000", -- 0x0E7: RET
"111100" & X"000", -- 0x0E8: PUSH R00
"101000" & X"A00", -- 0x0E9: XIN R00, (0xA0)
"011001" & X"040", -- 0x0EA: AND R00, 0x04
"110001" & X"0E9", -- 0x0EB: JZ 0x0E9
"111101" & X"000", -- 0x0EC: POP R00
"111110" & X"000", -- 0x0ED: RET
"111011" & X"1F1", -- 0x0EE: CALL 0x1F1
"111011" & X"1AE", -- 0x0EF: CALL 0x1AE
"000010" & X"010", -- 0x0F0: MOV R00, R01
"111011" & X"1AE", -- 0x0F1: CALL 0x1AE
"111110" & X"000", -- 0x0F2: RET
"000011" & X"400", -- 0x0F3: MOV R00, 0x40
"111011" & X"197", -- 0x0F4: CALL 0x197
"000011" & X"E01", -- 0x0F5: MOV R01, 0xE0
"000011" & X"06F", -- 0x0F6: MOV R15, 0x06
"000011" & X"07E", -- 0x0F7: MOV R14, 0x07
"000010" & X"010", -- 0x0F8: MOV R00, R01
"111011" & X"1AE", -- 0x0F9: CALL 0x1AE
"010101" & X"01E", -- 0x0FA: DEC R14
"110010" & X"0F8", -- 0x0FB: JNZ 0x0F8
"000011" & X"000", -- 0x0FC: MOV R00, 0x00
"111011" & X"1AE", -- 0x0FD: CALL 0x1AE
"000011" & X"010", -- 0x0FE: MOV R00, 0x01
"011111" & X"000", -- 0x0FF: SHR R00
"100011" & X"001", -- 0x100: RORC R01
"010101" & X"01F", -- 0x101: DEC R15
"110010" & X"0F7", -- 0x102: JNZ 0x0F7
"111110" & X"000", -- 0x103: RET
"111100" & X"000", -- 0x104: PUSH R00
"111100" & X"001", -- 0x105: PUSH R01
"111100" & X"00F", -- 0x106: PUSH R15
"001010" & X"0E0", -- 0x107: MOVC R00, (0x0E)
"001010" & X"0F1", -- 0x108: MOVC R01, (0x0F)
"010101" & X"010", -- 0x109: DEC R00
"010111" & X"001", -- 0x10A: SUBC R01, 0x00
"001101" & X"0E0", -- 0x10B: MOVC (0x0E), R00
"001101" & X"0F1", -- 0x10C: MOVC (0x0F), R01
"001111" & X"001", -- 0x10D: TST R01
"110001" & X"110", -- 0x10E: JZ 0x110
"110000" & X"141", -- 0x10F: JMP 0x141
"001111" & X"000", -- 0x110: TST R00
"110001" & X"113", -- 0x111: JZ 0x113
"110000" & X"141", -- 0x112: JMP 0x141
"000011" & X"800", -- 0x113: MOV R00, 0x80
"000011" & X"001", -- 0x114: MOV R01, 0x00
"001101" & X"0E0", -- 0x115: MOVC (0x0E), R00
"001101" & X"0F1", -- 0x116: MOVC (0x0F), R01
"000011" & X"0BF", -- 0x117: MOV R15, 0x0B
"000011" & X"000", -- 0x118: MOV R00, 0x00
"001010" & X"0B1", -- 0x119: MOVC R01, (0x0B)
"001111" & X"801", -- 0x11A: CMP R01, 0x80
"111000" & X"122", -- 0x11B: JGE 0x122
"001010" & X"0B1", -- 0x11C: MOVC R01, (0x0B)
"001010" & X"0A0", -- 0x11D: MOVC R00, (0x0A)
"011111" & X"001", -- 0x11E: SHR R01
"100011" & X"000", -- 0x11F: RORC R00
"010101" & X"01F", -- 0x120: DEC R15
"110010" & X"11E", -- 0x121: JNZ 0x11E
"001101" & X"060", -- 0x122: MOVC (0x06), R00
"000011" & X"0BF", -- 0x123: MOV R15, 0x0B
"000011" & X"000", -- 0x124: MOV R00, 0x00
"001010" & X"0D1", -- 0x125: MOVC R01, (0x0D)
"001111" & X"801", -- 0x126: CMP R01, 0x80
"111000" & X"12E", -- 0x127: JGE 0x12E
"001010" & X"0C0", -- 0x128: MOVC R00, (0x0C)
"001010" & X"0D1", -- 0x129: MOVC R01, (0x0D)
"011111" & X"001", -- 0x12A: SHR R01
"100011" & X"000", -- 0x12B: RORC R00
"010101" & X"01F", -- 0x12C: DEC R15
"110010" & X"12A", -- 0x12D: JNZ 0x12A
"001101" & X"070", -- 0x12E: MOVC (0x07), R00
"001010" & X"060", -- 0x12F: MOVC R00, (0x06)
"001010" & X"081", -- 0x130: MOVC R01, (0x08)
"001111" & X"001", -- 0x131: TST R01
"110001" & X"134", -- 0x132: JZ 0x134
"010101" & X"011", -- 0x133: DEC R01
"001110" & X"010", -- 0x134: CMP R00, R01
"110101" & X"137", -- 0x135: JLT 0x137
"000010" & X"001", -- 0x136: MOV R01, R00
"001101" & X"081", -- 0x137: MOVC (0x08), R01
"001010" & X"070", -- 0x138: MOVC R00, (0x07)
"001010" & X"091", -- 0x139: MOVC R01, (0x09)
"001111" & X"001", -- 0x13A: TST R01
"110001" & X"13D", -- 0x13B: JZ 0x13D
"010101" & X"011", -- 0x13C: DEC R01
"001110" & X"010", -- 0x13D: CMP R00, R01
"110101" & X"140", -- 0x13E: JLT 0x140
"000010" & X"001", -- 0x13F: MOV R01, R00
"001101" & X"091", -- 0x140: MOVC (0x09), R01
"111101" & X"00F", -- 0x141: POP R15
"111101" & X"001", -- 0x142: POP R01
"111101" & X"000", -- 0x143: POP R00
"111110" & X"000", -- 0x144: RET
"111100" & X"00F", -- 0x145: PUSH R15
"000011" & X"0AF", -- 0x146: MOV R15, 0x0A
"111011" & X"14C", -- 0x147: CALL 0x14C
"010101" & X"01F", -- 0x148: DEC R15
"110010" & X"147", -- 0x149: JNZ 0x147
"111101" & X"00F", -- 0x14A: POP R15
"111110" & X"000", -- 0x14B: RET
"111100" & X"00F", -- 0x14C: PUSH R15
"000011" & X"0AF", -- 0x14D: MOV R15, 0x0A
"111011" & X"153", -- 0x14E: CALL 0x153
"010101" & X"01F", -- 0x14F: DEC R15
"110010" & X"14E", -- 0x150: JNZ 0x14E
"111101" & X"00F", -- 0x151: POP R15
"111110" & X"000", -- 0x152: RET
"111100" & X"00F", -- 0x153: PUSH R15
"000011" & X"0AF", -- 0x154: MOV R15, 0x0A
"111011" & X"15A", -- 0x155: CALL 0x15A
"010101" & X"01F", -- 0x156: DEC R15
"110010" & X"155", -- 0x157: JNZ 0x155
"111101" & X"00F", -- 0x158: POP R15
"111110" & X"000", -- 0x159: RET
"111100" & X"00F", -- 0x15A: PUSH R15
"000011" & X"0AF", -- 0x15B: MOV R15, 0x0A
"111011" & X"161", -- 0x15C: CALL 0x161
"010101" & X"01F", -- 0x15D: DEC R15
"110010" & X"15C", -- 0x15E: JNZ 0x15C
"111101" & X"00F", -- 0x15F: POP R15
"111110" & X"000", -- 0x160: RET
"111100" & X"00F", -- 0x161: PUSH R15
"000011" & X"0AF", -- 0x162: MOV R15, 0x0A
"111011" & X"168", -- 0x163: CALL 0x168
"010101" & X"01F", -- 0x164: DEC R15
"110010" & X"163", -- 0x165: JNZ 0x163
"111101" & X"00F", -- 0x166: POP R15
"111110" & X"000", -- 0x167: RET
"111100" & X"00F", -- 0x168: PUSH R15
"000011" & X"63F", -- 0x169: MOV R15, 0x63
"000000" & X"000", -- 0x16A: NOP
"000000" & X"000", -- 0x16B: NOP
"000000" & X"000", -- 0x16C: NOP
"010101" & X"01F", -- 0x16D: DEC R15
"110010" & X"16A", -- 0x16E: JNZ 0x16A
"111101" & X"00F", -- 0x16F: POP R15
"111110" & X"000", -- 0x170: RET
"111100" & X"00F", -- 0x171: PUSH R15
"000011" & X"09F", -- 0x172: MOV R15, 0x09
"000000" & X"000", -- 0x173: NOP
"000000" & X"000", -- 0x174: NOP
"000000" & X"000", -- 0x175: NOP
"010101" & X"01F", -- 0x176: DEC R15
"110010" & X"173", -- 0x177: JNZ 0x173
"111101" & X"00F", -- 0x178: POP R15
"111110" & X"000", -- 0x179: RET
"000011" & X"002", -- 0x17A: MOV R02, 0x00
"000011" & X"030", -- 0x17B: MOV R00, 0x03
"111011" & X"1C6", -- 0x17C: CALL 0x1C6
"111011" & X"153", -- 0x17D: CALL 0x153
"000011" & X"002", -- 0x17E: MOV R02, 0x00
"000011" & X"030", -- 0x17F: MOV R00, 0x03
"111011" & X"1C6", -- 0x180: CALL 0x1C6
"111011" & X"153", -- 0x181: CALL 0x153
"000011" & X"002", -- 0x182: MOV R02, 0x00
"000011" & X"020", -- 0x183: MOV R00, 0x02
"111011" & X"1C6", -- 0x184: CALL 0x1C6
"111011" & X"15A", -- 0x185: CALL 0x15A
"000011" & X"280", -- 0x186: MOV R00, 0x28
"111011" & X"197", -- 0x187: CALL 0x197
"000011" & X"0C0", -- 0x188: MOV R00, 0x0C
"111011" & X"197", -- 0x189: CALL 0x197
"000011" & X"060", -- 0x18A: MOV R00, 0x06
"111011" & X"197", -- 0x18B: CALL 0x197
"000011" & X"010", -- 0x18C: MOV R00, 0x01
"111011" & X"197", -- 0x18D: CALL 0x197
"111110" & X"000", -- 0x18E: RET
"111100" & X"000", -- 0x18F: PUSH R00
"111011" & X"1BA", -- 0x190: CALL 0x1BA
"011001" & X"800", -- 0x191: AND R00, 0x80
"110001" & X"195", -- 0x192: JZ 0x195
"111011" & X"171", -- 0x193: CALL 0x171
"110000" & X"190", -- 0x194: JMP 0x190
"111101" & X"000", -- 0x195: POP R00
"111110" & X"000", -- 0x196: RET
"111100" & X"002", -- 0x197: PUSH R02
"000011" & X"002", -- 0x198: MOV R02, 0x00
"111011" & X"1B3", -- 0x199: CALL 0x1B3
"111101" & X"002", -- 0x19A: POP R02
"111110" & X"000", -- 0x19B: RET
"111100" & X"000", -- 0x19C: PUSH R00
"000100" & X"010", -- 0x19D: MOVX R00, (R01)
"010001" & X"011", -- 0x19E: INC R01
"001111" & X"000", -- 0x19F: TST R00
"110001" & X"1A3", -- 0x1A0: JZ 0x1A3
"111011" & X"1AE", -- 0x1A1: CALL 0x1AE
"110000" & X"19D", -- 0x1A2: JMP 0x19D
"111101" & X"000", -- 0x1A3: POP R00
"111110" & X"000", -- 0x1A4: RET
"111100" & X"000", -- 0x1A5: PUSH R00
"001001" & X"010", -- 0x1A6: MOVC R00, (R01)
"010001" & X"011", -- 0x1A7: INC R01
"001111" & X"000", -- 0x1A8: TST R00
"110001" & X"1AC", -- 0x1A9: JZ 0x1AC
"111011" & X"1AE", -- 0x1AA: CALL 0x1AE
"110000" & X"1A6", -- 0x1AB: JMP 0x1A6
"111101" & X"000", -- 0x1AC: POP R00
"111110" & X"000", -- 0x1AD: RET
"111100" & X"002", -- 0x1AE: PUSH R02
"000011" & X"402", -- 0x1AF: MOV R02, 0x40
"111011" & X"1B3", -- 0x1B0: CALL 0x1B3
"111101" & X"002", -- 0x1B1: POP R02
"111110" & X"000", -- 0x1B2: RET
"111011" & X"18F", -- 0x1B3: CALL 0x18F
"111100" & X"000", -- 0x1B4: PUSH R00
"101010" & X"000", -- 0x1B5: SWAP R00
"111011" & X"1C6", -- 0x1B6: CALL 0x1C6
"111101" & X"000", -- 0x1B7: POP R00
"111011" & X"1C6", -- 0x1B8: CALL 0x1C6
"111110" & X"000", -- 0x1B9: RET
"111100" & X"002", -- 0x1BA: PUSH R02
"000011" & X"002", -- 0x1BB: MOV R02, 0x00
"111011" & X"1BF", -- 0x1BC: CALL 0x1BF
"111101" & X"002", -- 0x1BD: POP R02
"111110" & X"000", -- 0x1BE: RET
"111011" & X"1D9", -- 0x1BF: CALL 0x1D9
"101010" & X"000", -- 0x1C0: SWAP R00
"111100" & X"000", -- 0x1C1: PUSH R00
"111011" & X"1D9", -- 0x1C2: CALL 0x1D9
"111101" & X"002", -- 0x1C3: POP R02
"011010" & X"020", -- 0x1C4: OR R00, R02
"111110" & X"000", -- 0x1C5: RET
"111100" & X"001", -- 0x1C6: PUSH R01
"011001" & X"0F0", -- 0x1C7: AND R00, 0x0F
"000010" & X"001", -- 0x1C8: MOV R01, R00
"011010" & X"021", -- 0x1C9: OR R01, R02
"100100" & X"081", -- 0x1CA: XOUT (0x08), R01
"111011" & X"171", -- 0x1CB: CALL 0x171
"000010" & X"001", -- 0x1CC: MOV R01, R00
"011010" & X"021", -- 0x1CD: OR R01, R02
"011011" & X"801", -- 0x1CE: OR R01, 0x80
"100100" & X"081", -- 0x1CF: XOUT (0x08), R01
"111011" & X"171", -- 0x1D0: CALL 0x171
"000010" & X"001", -- 0x1D1: MOV R01, R00
"011010" & X"021", -- 0x1D2: OR R01, R02
"100100" & X"081", -- 0x1D3: XOUT (0x08), R01
"111011" & X"171", -- 0x1D4: CALL 0x171
"011011" & X"201", -- 0x1D5: OR R01, 0x20
"100100" & X"081", -- 0x1D6: XOUT (0x08), R01
"111101" & X"001", -- 0x1D7: POP R01
"111110" & X"000", -- 0x1D8: RET
"111100" & X"001", -- 0x1D9: PUSH R01
"000011" & X"201", -- 0x1DA: MOV R01, 0x20
"011010" & X"021", -- 0x1DB: OR R01, R02
"100100" & X"081", -- 0x1DC: XOUT (0x08), R01
"111011" & X"171", -- 0x1DD: CALL 0x171
"000011" & X"201", -- 0x1DE: MOV R01, 0x20
"011010" & X"021", -- 0x1DF: OR R01, R02
"011011" & X"801", -- 0x1E0: OR R01, 0x80
"100100" & X"081", -- 0x1E1: XOUT (0x08), R01
"111011" & X"171", -- 0x1E2: CALL 0x171
"101000" & X"080", -- 0x1E3: XIN R00, (0x08)
"011001" & X"0F0", -- 0x1E4: AND R00, 0x0F
"000011" & X"201", -- 0x1E5: MOV R01, 0x20
"011010" & X"021", -- 0x1E6: OR R01, R02
"100100" & X"081", -- 0x1E7: XOUT (0x08), R01
"111011" & X"171", -- 0x1E8: CALL 0x171
"111101" & X"001", -- 0x1E9: POP R01
"111110" & X"000", -- 0x1EA: RET
"011001" & X"0F0", -- 0x1EB: AND R00, 0x0F
"001111" & X"0A0", -- 0x1EC: CMP R00, 0x0A
"110101" & X"1EF", -- 0x1ED: JLT 0x1EF
"010001" & X"070", -- 0x1EE: ADD R00, 0x07
"010001" & X"300", -- 0x1EF: ADD R00, 0x30
"111110" & X"000", -- 0x1F0: RET
"111100" & X"000", -- 0x1F1: PUSH R00
"111011" & X"1EB", -- 0x1F2: CALL 0x1EB
"000010" & X"001", -- 0x1F3: MOV R01, R00
"111101" & X"000", -- 0x1F4: POP R00
"101010" & X"000", -- 0x1F5: SWAP R00
"111011" & X"1EB", -- 0x1F6: CALL 0x1EB
"111110" & X"000" -- 0x1F7: RET
);
begin
PROM_READ:
process(clk, ce)
begin
if rising_edge(clk) and ce = '1' then
dout <= imem_rom(to_integer(addr));
end if;
end process;
end test;
projects/ac97_Controller/src/test_irom_ld.vhdl
+1182
View File
File diff suppressed because it is too large Load Diff
projects/ac97_Controller/src/test_xrom.vhdl
+318
View File
@@ -0,0 +1,318 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.cpu_pkg.all;
-- JASM_ROM_INSERT_HERE
ENTITY xrom IS
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in dmem_addr_t;
dout : out dmem_data_t
);
END xrom;
ARCHITECTURE test OF xrom IS
type xmem_rom_t is array (0 to 255) of dmem_data_t;
-- Assembled from test.jsm
constant xmem_rom : xmem_rom_t :=
(
X"41", -- 0x00
X"43", -- 0x01
X"27", -- 0x02
X"39", -- 0x03
X"37", -- 0x04
X"20", -- 0x05
X"54", -- 0x06
X"65", -- 0x07
X"73", -- 0x08
X"74", -- 0x09
X"20", -- 0x0A
X"56", -- 0x0B
X"31", -- 0x0C
X"2E", -- 0x0D
X"32", -- 0x0E
X"00", -- 0x0F
X"00", -- 0x10
X"2A", -- 0x11
X"00", -- 0x12
X"1A", -- 0x13
X"00", -- 0x14
X"1C", -- 0x15
X"00", -- 0x16
X"2C", -- 0x17
X"00", -- 0x18
X"32", -- 0x19
X"00", -- 0x1A
X"20", -- 0x1B
X"00", -- 0x1C
X"02", -- 0x1D
X"00", -- 0x1E
X"04", -- 0x1F
X"00", -- 0x20
X"18", -- 0x21
X"01", -- 0x22
X"00", -- 0x23
X"04", -- 0x24
X"04", -- 0x25
X"00", -- 0x26
X"00", -- 0x27
X"80", -- 0x28
X"BB", -- 0x29
X"80", -- 0x2A
X"BB", -- 0x2B
X"00", -- 0x2C
X"80", -- 0x2D
X"00", -- 0x2E
X"00", -- 0x2F
X"00", -- 0x30
X"00", -- 0x31
X"0A", -- 0x32
X"0A", -- 0x33
X"00", -- 0x34
X"00", -- 0x35
X"00", -- 0x36
X"00", -- 0x37
X"00", -- 0x38
X"00", -- 0x39
X"00", -- 0x3A
X"00", -- 0x3B
X"00", -- 0x3C
X"00", -- 0x3D
X"00", -- 0x3E
X"00", -- 0x3F
X"00", -- 0x40
X"00", -- 0x41
X"00", -- 0x42
X"00", -- 0x43
X"00", -- 0x44
X"00", -- 0x45
X"00", -- 0x46
X"00", -- 0x47
X"00", -- 0x48
X"00", -- 0x49
X"00", -- 0x4A
X"00", -- 0x4B
X"00", -- 0x4C
X"00", -- 0x4D
X"00", -- 0x4E
X"00", -- 0x4F
X"00", -- 0x50
X"00", -- 0x51
X"00", -- 0x52
X"00", -- 0x53
X"00", -- 0x54
X"00", -- 0x55
X"00", -- 0x56
X"00", -- 0x57
X"00", -- 0x58
X"00", -- 0x59
X"00", -- 0x5A
X"00", -- 0x5B
X"00", -- 0x5C
X"00", -- 0x5D
X"00", -- 0x5E
X"00", -- 0x5F
X"00", -- 0x60
X"00", -- 0x61
X"00", -- 0x62
X"00", -- 0x63
X"00", -- 0x64
X"00", -- 0x65
X"00", -- 0x66
X"00", -- 0x67
X"00", -- 0x68
X"00", -- 0x69
X"00", -- 0x6A
X"00", -- 0x6B
X"00", -- 0x6C
X"00", -- 0x6D
X"00", -- 0x6E
X"00", -- 0x6F
X"00", -- 0x70
X"00", -- 0x71
X"00", -- 0x72
X"00", -- 0x73
X"00", -- 0x74
X"00", -- 0x75
X"00", -- 0x76
X"00", -- 0x77
X"00", -- 0x78
X"00", -- 0x79
X"00", -- 0x7A
X"00", -- 0x7B
X"00", -- 0x7C
X"00", -- 0x7D
X"00", -- 0x7E
X"00", -- 0x7F
X"00", -- 0x80
X"00", -- 0x81
X"00", -- 0x82
X"00", -- 0x83
X"00", -- 0x84
X"00", -- 0x85
X"00", -- 0x86
X"00", -- 0x87
X"00", -- 0x88
X"00", -- 0x89
X"00", -- 0x8A
X"00", -- 0x8B
X"00", -- 0x8C
X"00", -- 0x8D
X"00", -- 0x8E
X"00", -- 0x8F
X"00", -- 0x90
X"00", -- 0x91
X"00", -- 0x92
X"00", -- 0x93
X"00", -- 0x94
X"00", -- 0x95
X"00", -- 0x96
X"00", -- 0x97
X"00", -- 0x98
X"00", -- 0x99
X"00", -- 0x9A
X"00", -- 0x9B
X"00", -- 0x9C
X"00", -- 0x9D
X"00", -- 0x9E
X"00", -- 0x9F
X"00", -- 0xA0
X"00", -- 0xA1
X"00", -- 0xA2
X"00", -- 0xA3
X"00", -- 0xA4
X"00", -- 0xA5
X"00", -- 0xA6
X"00", -- 0xA7
X"00", -- 0xA8
X"00", -- 0xA9
X"00", -- 0xAA
X"00", -- 0xAB
X"00", -- 0xAC
X"00", -- 0xAD
X"00", -- 0xAE
X"00", -- 0xAF
X"00", -- 0xB0
X"00", -- 0xB1
X"00", -- 0xB2
X"00", -- 0xB3
X"00", -- 0xB4
X"00", -- 0xB5
X"00", -- 0xB6
X"00", -- 0xB7
X"00", -- 0xB8
X"00", -- 0xB9
X"00", -- 0xBA
X"00", -- 0xBB
X"00", -- 0xBC
X"00", -- 0xBD
X"00", -- 0xBE
X"00", -- 0xBF
X"00", -- 0xC0
X"00", -- 0xC1
X"00", -- 0xC2
X"00", -- 0xC3
X"00", -- 0xC4
X"00", -- 0xC5
X"00", -- 0xC6
X"00", -- 0xC7
X"00", -- 0xC8
X"00", -- 0xC9
X"00", -- 0xCA
X"00", -- 0xCB
X"00", -- 0xCC
X"00", -- 0xCD
X"00", -- 0xCE
X"00", -- 0xCF
X"00", -- 0xD0
X"00", -- 0xD1
X"00", -- 0xD2
X"00", -- 0xD3
X"00", -- 0xD4
X"00", -- 0xD5
X"00", -- 0xD6
X"00", -- 0xD7
X"00", -- 0xD8
X"00", -- 0xD9
X"00", -- 0xDA
X"00", -- 0xDB
X"00", -- 0xDC
X"00", -- 0xDD
X"00", -- 0xDE
X"00", -- 0xDF
X"00", -- 0xE0
X"00", -- 0xE1
X"00", -- 0xE2
X"00", -- 0xE3
X"00", -- 0xE4
X"00", -- 0xE5
X"00", -- 0xE6
X"00", -- 0xE7
X"00", -- 0xE8
X"00", -- 0xE9
X"00", -- 0xEA
X"00", -- 0xEB
X"00", -- 0xEC
X"00", -- 0xED
X"00", -- 0xEE
X"00", -- 0xEF
X"00", -- 0xF0
X"00", -- 0xF1
X"00", -- 0xF2
X"00", -- 0xF3
X"00", -- 0xF4
X"00", -- 0xF5
X"00", -- 0xF6
X"00", -- 0xF7
X"00", -- 0xF8
X"00", -- 0xF9
X"00", -- 0xFA
X"00", -- 0xFB
X"00", -- 0xFC
X"00", -- 0xFD
X"00", -- 0xFE
X"00" -- 0xFF
);
begin
PROM_READ:
process(clk, ce)
begin
if rising_edge(clk) and ce = '1' then
dout <= xmem_rom(to_integer(addr));
end if;
end process;
end test;
projects/ac97_Controller/src/test_xrom_ld.vhdl
+414
View File
@@ -0,0 +1,414 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: loadable ROM
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.cpu_pkg.all;
ENTITY xrom IS
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in dmem_addr_t;
dout : out dmem_data_t
);
END xrom;
ARCHITECTURE loadable OF xrom IS
-- JASM_ROM_INSERT_HERE
-- Assembled from test.jsm
type xmem_rom_t is array (0 to 255) of dmem_data_t;
signal xmem_rom : xmem_rom_t :=
(
X"41", -- 0x00
X"43", -- 0x01
X"27", -- 0x02
X"39", -- 0x03
X"37", -- 0x04
X"20", -- 0x05
X"54", -- 0x06
X"65", -- 0x07
X"73", -- 0x08
X"74", -- 0x09
X"20", -- 0x0A
X"56", -- 0x0B
X"31", -- 0x0C
X"2E", -- 0x0D
X"32", -- 0x0E
X"00", -- 0x0F
X"00", -- 0x10
X"2A", -- 0x11
X"00", -- 0x12
X"1A", -- 0x13
X"00", -- 0x14
X"1C", -- 0x15
X"00", -- 0x16
X"2C", -- 0x17
X"00", -- 0x18
X"32", -- 0x19
X"00", -- 0x1A
X"20", -- 0x1B
X"00", -- 0x1C
X"02", -- 0x1D
X"00", -- 0x1E
X"04", -- 0x1F
X"00", -- 0x20
X"18", -- 0x21
X"01", -- 0x22
X"00", -- 0x23
X"04", -- 0x24
X"04", -- 0x25
X"00", -- 0x26
X"00", -- 0x27
X"80", -- 0x28
X"BB", -- 0x29
X"80", -- 0x2A
X"BB", -- 0x2B
X"00", -- 0x2C
X"80", -- 0x2D
X"00", -- 0x2E
X"00", -- 0x2F
X"00", -- 0x30
X"00", -- 0x31
X"0A", -- 0x32
X"0A", -- 0x33
X"00", -- 0x34
X"00", -- 0x35
X"00", -- 0x36
X"00", -- 0x37
X"00", -- 0x38
X"00", -- 0x39
X"00", -- 0x3A
X"00", -- 0x3B
X"00", -- 0x3C
X"00", -- 0x3D
X"00", -- 0x3E
X"00", -- 0x3F
X"00", -- 0x40
X"00", -- 0x41
X"00", -- 0x42
X"00", -- 0x43
X"00", -- 0x44
X"00", -- 0x45
X"00", -- 0x46
X"00", -- 0x47
X"00", -- 0x48
X"00", -- 0x49
X"00", -- 0x4A
X"00", -- 0x4B
X"00", -- 0x4C
X"00", -- 0x4D
X"00", -- 0x4E
X"00", -- 0x4F
X"00", -- 0x50
X"00", -- 0x51
X"00", -- 0x52
X"00", -- 0x53
X"00", -- 0x54
X"00", -- 0x55
X"00", -- 0x56
X"00", -- 0x57
X"00", -- 0x58
X"00", -- 0x59
X"00", -- 0x5A
X"00", -- 0x5B
X"00", -- 0x5C
X"00", -- 0x5D
X"00", -- 0x5E
X"00", -- 0x5F
X"00", -- 0x60
X"00", -- 0x61
X"00", -- 0x62
X"00", -- 0x63
X"00", -- 0x64
X"00", -- 0x65
X"00", -- 0x66
X"00", -- 0x67
X"00", -- 0x68
X"00", -- 0x69
X"00", -- 0x6A
X"00", -- 0x6B
X"00", -- 0x6C
X"00", -- 0x6D
X"00", -- 0x6E
X"00", -- 0x6F
X"00", -- 0x70
X"00", -- 0x71
X"00", -- 0x72
X"00", -- 0x73
X"00", -- 0x74
X"00", -- 0x75
X"00", -- 0x76
X"00", -- 0x77
X"00", -- 0x78
X"00", -- 0x79
X"00", -- 0x7A
X"00", -- 0x7B
X"00", -- 0x7C
X"00", -- 0x7D
X"00", -- 0x7E
X"00", -- 0x7F
X"00", -- 0x80
X"00", -- 0x81
X"00", -- 0x82
X"00", -- 0x83
X"00", -- 0x84
X"00", -- 0x85
X"00", -- 0x86
X"00", -- 0x87
X"00", -- 0x88
X"00", -- 0x89
X"00", -- 0x8A
X"00", -- 0x8B
X"00", -- 0x8C
X"00", -- 0x8D
X"00", -- 0x8E
X"00", -- 0x8F
X"00", -- 0x90
X"00", -- 0x91
X"00", -- 0x92
X"00", -- 0x93
X"00", -- 0x94
X"00", -- 0x95
X"00", -- 0x96
X"00", -- 0x97
X"00", -- 0x98
X"00", -- 0x99
X"00", -- 0x9A
X"00", -- 0x9B
X"00", -- 0x9C
X"00", -- 0x9D
X"00", -- 0x9E
X"00", -- 0x9F
X"00", -- 0xA0
X"00", -- 0xA1
X"00", -- 0xA2
X"00", -- 0xA3
X"00", -- 0xA4
X"00", -- 0xA5
X"00", -- 0xA6
X"00", -- 0xA7
X"00", -- 0xA8
X"00", -- 0xA9
X"00", -- 0xAA
X"00", -- 0xAB
X"00", -- 0xAC
X"00", -- 0xAD
X"00", -- 0xAE
X"00", -- 0xAF
X"00", -- 0xB0
X"00", -- 0xB1
X"00", -- 0xB2
X"00", -- 0xB3
X"00", -- 0xB4
X"00", -- 0xB5
X"00", -- 0xB6
X"00", -- 0xB7
X"00", -- 0xB8
X"00", -- 0xB9
X"00", -- 0xBA
X"00", -- 0xBB
X"00", -- 0xBC
X"00", -- 0xBD
X"00", -- 0xBE
X"00", -- 0xBF
X"00", -- 0xC0
X"00", -- 0xC1
X"00", -- 0xC2
X"00", -- 0xC3
X"00", -- 0xC4
X"00", -- 0xC5
X"00", -- 0xC6
X"00", -- 0xC7
X"00", -- 0xC8
X"00", -- 0xC9
X"00", -- 0xCA
X"00", -- 0xCB
X"00", -- 0xCC
X"00", -- 0xCD
X"00", -- 0xCE
X"00", -- 0xCF
X"00", -- 0xD0
X"00", -- 0xD1
X"00", -- 0xD2
X"00", -- 0xD3
X"00", -- 0xD4
X"00", -- 0xD5
X"00", -- 0xD6
X"00", -- 0xD7
X"00", -- 0xD8
X"00", -- 0xD9
X"00", -- 0xDA
X"00", -- 0xDB
X"00", -- 0xDC
X"00", -- 0xDD
X"00", -- 0xDE
X"00", -- 0xDF
X"00", -- 0xE0
X"00", -- 0xE1
X"00", -- 0xE2
X"00", -- 0xE3
X"00", -- 0xE4
X"00", -- 0xE5
X"00", -- 0xE6
X"00", -- 0xE7
X"00", -- 0xE8
X"00", -- 0xE9
X"00", -- 0xEA
X"00", -- 0xEB
X"00", -- 0xEC
X"00", -- 0xED
X"00", -- 0xEE
X"00", -- 0xEF
X"00", -- 0xF0
X"00", -- 0xF1
X"00", -- 0xF2
X"00", -- 0xF3
X"00", -- 0xF4
X"00", -- 0xF5
X"00", -- 0xF6
X"00", -- 0xF7
X"00", -- 0xF8
X"00", -- 0xF9
X"00", -- 0xFA
X"00", -- 0xFB
X"00", -- 0xFC
X"00", -- 0xFD
X"00", -- 0xFE
X"00" -- 0xFF
);
signal jtag_ld_clk : STD_LOGIC;
signal jtag_ld_we : STD_LOGIC;
signal jtag_ld_addr : dmem_addr_t;
signal jtag_ld_dout : dmem_data_t;
signal jtag_ld_din : dmem_data_t;
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (15 downto 0);
constant id : unsigned (15 downto 0) := X"BEEF";
begin
--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
i00_BUFG : BUFG
port map
(
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map
(
O => bs_update1,
I => bs_update0
);
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
generic map
(
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
)
port map
(
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
jtag_ld_clk <= bs_update1;
jtag_ld_we <= bs_sel;
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (bs_rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if bs_rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
-- user_rego <= id;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- ROM Read/Write
--------------------------------------------------------------------------
PROM_READ:
process(clk, ce)
begin
if rising_edge(clk) and ce = '1' then
dout <= xmem_rom(to_integer(addr));
end if;
end process;
PROM_WRITE:
process(jtag_ld_clk, jtag_ld_we)
begin
if rising_edge(jtag_ld_clk) then
if jtag_ld_we = '1' then
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
else
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
end if;
end if;
end process;
--------------------------------------------------------------------------
end loadable;