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- minor changes

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git-svn-id: http://moon:8086/svn/vhdl/trunk@864 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-07 11:20:44 +00:00
parent bb41db0f76
commit 668ab68b8b
1 changed files with 45 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/emac/src/tb_emac_top_jb.vhd
+45 -30
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@@ -32,7 +32,7 @@ END tb_emac_top_jb;
ARCHITECTURE behavior OF tb_emac_top_jb IS ARCHITECTURE behavior OF tb_emac_top_jb IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 7.7 ns; constant MII_CLK_PERIOD : time := 38.7 ns;
signal CLK : std_logic := '1'; signal CLK : std_logic := '1';
signal RST : std_logic := '1'; signal RST : std_logic := '1';
@@ -50,6 +50,8 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
signal DAT_I : unsigned(31 downto 0) := (others => '-'); signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-'); signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-'); signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
signal status_reg : unsigned(31 downto 0) := (others => '0');
signal size_reg : unsigned(31 downto 0) := (others => '0');
-- MII signals -- MII signals
signal mii_rx_clk_board : std_logic := '1'; signal mii_rx_clk_board : std_logic := '1';
@@ -71,7 +73,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
signal pktgen_tx : unsigned(7 downto 0); signal pktgen_tx : unsigned(7 downto 0);
signal pktgen_tx_en : std_logic; signal pktgen_tx_en : std_logic;
signal pktgen_tx_er : std_logic; signal pktgen_tx_er : std_logic;
signal pktgen_rst : std_logic := '1'; signal pktgen_en : std_logic := '0';
signal dat_o_cnt_en : std_logic := '0'; signal dat_o_cnt_en : std_logic := '0';
signal dat_o_cnt_rst : std_logic := '1'; signal dat_o_cnt_rst : std_logic := '1';
@@ -81,6 +83,12 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free); type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
signal emac_action : emac_action_t; signal emac_action : emac_action_t;
constant RX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0000";
constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_0010";
BEGIN BEGIN
inst_emac_top_jb : entity work.emac_top_jb inst_emac_top_jb : entity work.emac_top_jb
@@ -132,7 +140,8 @@ inst_pkt_gen : entity work.pkt_gen
PORT MAP PORT MAP
( (
clk => CLK, clk => CLK,
rst => pktgen_rst, rst => RST,
en => pktgen_en,
mii_tx_clk => mii_tx_clk_board, mii_tx_clk => mii_tx_clk_board,
mii_tx_en => pktgen_tx_en, mii_tx_en => pktgen_tx_en,
mii_tx_er => pktgen_tx_er, mii_tx_er => pktgen_tx_er,
@@ -196,10 +205,10 @@ STIMULUS: process
emac_action <= emac_alloc; emac_action <= emac_alloc;
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= to_unsigned(size, 16) & X"55AA"; DAT_I <= to_unsigned(size, 32);
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= X"0000_0004"; ADDR_I <= TX_SIZE_REG_ADDR;
check_alloc_ok: check_alloc_ok:
while(true) loop while(true) loop
@@ -208,31 +217,33 @@ STIMULUS: process
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0200_0000" or (not X"0103_0000" and DAT_O_reg); DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= TX_STATUS_REG_ADDR;
check_bsy: check_bsy:
while (true) loop while (true) loop
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK); wait until rising_edge(CLK);
if DAT_O_reg(25) = '0' then if status_reg(17) = '0' then
exit check_bsy; exit check_bsy;
end if; end if;
end loop; end loop;
if DAT_O_reg(24) = '1' then if status_reg(16) = '1' then
exit check_alloc_ok; exit check_alloc_ok;
end if; end if;
end loop; end loop;
@@ -253,15 +264,16 @@ STIMULUS: process
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0100_0000" or (not X"0203_0000" and DAT_O_reg); DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
WE_I <= '0'; WE_I <= '0';
@@ -286,7 +298,7 @@ STIMULUS: process
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
data := X"00"; data := X"00";
ADDR_I <= X"0000_0008"; ADDR_I <= DATA_REG_ADDR;
WE_I <= '1'; WE_I <= '1';
for i in 1 to num_words loop for i in 1 to num_words loop
STB_I <= '1'; STB_I <= '1';
@@ -324,12 +336,13 @@ STIMULUS: process
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK); wait until rising_edge(CLK);
if DAT_O_reg(17) = '1' and DAT_O_reg(16) = '1' then if status_reg(17) = '1' and status_reg(16) = '1' then
exit check_data_avail; exit check_data_avail;
end if; end if;
end loop; end loop;
@@ -340,10 +353,11 @@ STIMULUS: process
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0004"; ADDR_I <= RX_SIZE_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
size_reg <= DAT_O;
wait until rising_edge(CLK); wait until rising_edge(CLK);
-- set packet request -- set packet request
@@ -351,15 +365,16 @@ STIMULUS: process
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0002_0000" or (not X"0301_0000" and DAT_O_reg); DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
WE_I <= '0'; WE_I <= '0';
@@ -368,7 +383,7 @@ STIMULUS: process
-- Read RX data -- Read RX data
size := size_in; size := size_in;
if (size_in = 0) then if (size_in = 0) then
size := to_integer(DAT_O_reg(15 downto 0)); size := to_integer(size_reg(15 downto 0));
end if; end if;
if (size mod 4) = 0 then if (size mod 4) = 0 then
@@ -381,8 +396,7 @@ STIMULUS: process
dat_o_cnt_en <= '1'; dat_o_cnt_en <= '1';
CYC_I <= '1'; CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
data := X"00"; ADDR_I <= DATA_REG_ADDR;
ADDR_I <= X"0000_0008";
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
for i in 1 to num_words loop for i in 1 to num_words loop
@@ -406,15 +420,16 @@ STIMULUS: process
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0'; WE_I <= '0';
STB_I <= '1'; STB_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1'; wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0001_0000" or (not X"0302_0000" and DAT_O_reg); DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
STB_I <= '1'; STB_I <= '1';
WE_I <= '1'; WE_I <= '1';
ADDR_I <= X"0000_0000"; ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1'; wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0'; STB_I <= '0';
WE_I <= '0'; WE_I <= '0';
@@ -554,15 +569,15 @@ STIMULUS: process
wait for 6000*CLK_PERIOD; wait for 6000*CLK_PERIOD;
loop_back_en <= '0'; loop_back_en <= '0';
pktgen_rst <= '0'; pktgen_en <= '1';
pkt_count <= 0; pkt_count <= 0;
for i in 1 to 500 loop for i in 1 to 500 loop
wait for 1 us; wait for 60 us;
emac_read (0); emac_read (0);
emac_free; emac_free;
pkt_count <= pkt_count + 1; pkt_count <= pkt_count + 1;
end loop; end loop;
pktgen_rst <= '1'; pktgen_en <= '0';
emac_read (0); emac_read (0);
emac_free; emac_free;