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cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@914 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-05-15 16:00:13 +00:00
parent dff1254bd9
commit 66514fbf7c
3 changed files with 29 additions and 82 deletions
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lib/VGA_ctrl/src/align.vhd
+10 -28
View File
@@ -8,8 +8,7 @@ ENTITY align IS
Generic Generic
( (
data_width : natural := 32; data_width : natural := 32;
aggregate_size : natural := 8; aggregate_size : natural := 8
allow_partial_valid : boolean := false
); );
Port Port
( (
@@ -18,12 +17,11 @@ ENTITY align IS
ce : in STD_LOGIC; ce : in STD_LOGIC;
eb : in STD_LOGIC; eb : in STD_LOGIC;
offset : in unsigned(NextExpBaseTwo(data_width/aggregate_size)-1 downto 0); offset : in unsigned(NextExpBaseTwo(data_width/aggregate_size)-1 downto 0);
din_last_vld : in STD_LOGIC;
din_vld : in STD_LOGIC; din_vld : in STD_LOGIC;
din : in unsigned(data_width-1 downto 0); din : in unsigned(data_width-1 downto 0);
dout_vld : out STD_LOGIC; dout_vld : out STD_LOGIC;
dout : out unsigned(data_width-1 downto 0); dout : out unsigned(data_width-1 downto 0);
dout_be : out unsigned(data_width/aggregate_size-1 downto 0) byte_en : out unsigned (data_width/aggregate_size-1 downto 0)
); );
END align; END align;
@@ -41,8 +39,6 @@ ARCHITECTURE behavior OF align IS
signal reg_be : unsigned(data_width/aggregate_size-1 downto 0); signal reg_be : unsigned(data_width/aggregate_size-1 downto 0);
signal data_vld : std_logic; signal data_vld : std_logic;
signal shift_din_vld : std_logic;
signal last_vld : unsigned(NextExpBaseTwo(data_width/aggregate_size)-1 downto 0);
type byte_en_rom_t is array (0 to 2*data_width/aggregate_size-1) of unsigned (data_width/aggregate_size-1 downto 0); type byte_en_rom_t is array (0 to 2*data_width/aggregate_size-1) of unsigned (data_width/aggregate_size-1 downto 0);
@@ -72,17 +68,16 @@ ARCHITECTURE behavior OF align IS
return result; return result;
end gen_byte_en_rom; end gen_byte_en_rom;
signal byte_en_rom : byte_en_rom_t := gen_byte_en_rom(data_width/aggregate_size); signal byte_en_rom : byte_en_rom_t := gen_byte_en_rom(data_width/aggregate_size);
signal byte_en : unsigned (data_width/aggregate_size-1 downto 0); signal be : unsigned (data_width/aggregate_size-1 downto 0);
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
byte_en <= byte_en_rom(to_integer(not eb & offset)); be <= byte_en_rom(to_integer(not eb & offset));
byte_en <= be;
dout <= reg; dout <= reg;
dout_be <= reg_be;
dout_vld <= data_vld; dout_vld <= data_vld;
shift_din_vld <= din_vld;
inst_shifter : entity work.shifter inst_shifter : entity work.shifter
GENERIC MAP GENERIC MAP
@@ -97,7 +92,7 @@ inst_shifter : entity work.shifter
clk => clk, clk => clk,
ce => ce, ce => ce,
sa => to_integer(offset), sa => to_integer(offset),
din_vld => shift_din_vld, din_vld => din_vld,
din => din, din => din,
dout_vld => shift_vld, dout_vld => shift_vld,
dout => shift_dout dout => shift_dout
@@ -111,15 +106,9 @@ proc_data_valid:
if rst = '1' then if rst = '1' then
reg0_vld <= '0'; reg0_vld <= '0';
data_vld <= '0'; data_vld <= '0';
last_vld <= (others => '0');
elsif ce = '1' then elsif ce = '1' then
last_vld <= last_vld(last_vld'left-1 downto 0) & din_last_vld;
reg0_vld <= shift_vld; reg0_vld <= shift_vld;
if offset /= (NextExpBaseTwo(data_width/aggregate_size)-1 downto 0 => '0') and not allow_partial_valid then data_vld <= shift_vld;
data_vld <= reg_vld and (shift_vld and not last_vld(last_vld'left));
else
data_vld <= shift_vld or last_vld(last_vld'left);
end if;
end if; end if;
end if; end if;
end process; end process;
@@ -141,21 +130,14 @@ proc_blit_dst_combine:
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
reg_be <= (others => '0');
reg_vld <= '0'; reg_vld <= '0';
elsif ce = '1' then elsif ce = '1' then
if reg0_vld = '1' or shift_vld = '1' then if reg0_vld = '1' or shift_vld = '1' then
reg_vld <= not last_vld(last_vld'left); reg_vld <= '1';
reg <= reg0; reg <= reg0;
if reg_vld = '0' or last_vld(last_vld'left) = '1' then
reg_be <= not byte_en and (data_width/aggregate_size-1 downto 0 => reg0_vld);
else
reg_be <= not byte_en;
end if;
if shift_vld = '1' then if shift_vld = '1' then
for i in 0 to data_width/aggregate_size-1 loop for i in 0 to data_width/aggregate_size-1 loop
if byte_en(i) = '1' then if be(i) = '1' then
reg_be(i) <= '1';
reg(aggregate_size*(i+1)-1 downto aggregate_size*i) <= shift_dout(aggregate_size*(i+1)-1 downto aggregate_size*i); reg(aggregate_size*(i+1)-1 downto aggregate_size*i) <= shift_dout(aggregate_size*(i+1)-1 downto aggregate_size*i);
end if; end if;
end loop; end loop;
lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+7 -5
View File
@@ -66,6 +66,7 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal rdy : std_logic := '0'; signal rdy : std_logic := '0';
signal read_reg : unsigned(31 downto 0) := (others => '-'); signal read_reg : unsigned(31 downto 0) := (others => '-');
signal const_color : unsigned(31 downto 0) := X"1111_1111";
-- VGA signals -- VGA signals
signal vga_clk : std_logic := '1'; signal vga_clk : std_logic := '1';
@@ -415,7 +416,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1'; STB_O <= '1';
WE_O <= '1'; WE_O <= '1';
SDAT_O <= X"0123_4567"; SDAT_O <= const_color;
ADDR_O <= X"0000_0054"; ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
@@ -519,7 +520,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1'; STB_O <= '1';
WE_O <= '1'; WE_O <= '1';
SDAT_O <= X"0123_4567"; SDAT_O <= const_color;
ADDR_O <= X"0000_0054"; ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
@@ -622,7 +623,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1'; STB_O <= '1';
WE_O <= '1'; WE_O <= '1';
SDAT_O <= X"0123_4567"; SDAT_O <= const_color;
ADDR_O <= X"0000_0054"; ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
@@ -725,7 +726,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1'; STB_O <= '1';
WE_O <= '1'; WE_O <= '1';
SDAT_O <= X"0123_4567"; SDAT_O <= const_color;
ADDR_O <= X"0000_0054"; ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
@@ -828,7 +829,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1'; STB_O <= '1';
WE_O <= '1'; WE_O <= '1';
SDAT_O <= X"0123_4567"; SDAT_O <= const_color;
ADDR_O <= X"0000_0054"; ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0'; STB_O <= '0';
@@ -872,6 +873,7 @@ STIMULUS: process
WE_O <= '0'; WE_O <= '0';
wait for 60000*CLK_PERIOD; wait for 60000*CLK_PERIOD;
const_color <= const_color + X"1111_1111";
end loop; end loop;
lib/VGA_ctrl/src/vga_frontend64.vhd
+12 -49
View File
@@ -186,7 +186,6 @@ architecture Behavioral of vga_frontend64 is
signal blit_src_addr : unsigned(2 downto 0); signal blit_src_addr : unsigned(2 downto 0);
signal blit_src_reg_vld : std_logic; signal blit_src_reg_vld : std_logic;
signal blit_src_reg : unsigned(63 downto 0); signal blit_src_reg : unsigned(63 downto 0);
signal blit_src_reg_be : unsigned(7 downto 0);
signal blit_src_rdy : std_logic; signal blit_src_rdy : std_logic;
signal blit_src_we : std_logic; signal blit_src_we : std_logic;
signal blit_src_re : std_logic; signal blit_src_re : std_logic;
@@ -218,6 +217,7 @@ architecture Behavioral of vga_frontend64 is
signal blit_dst_rdy : std_logic; signal blit_dst_rdy : std_logic;
signal blit_dst_we : std_logic; signal blit_dst_we : std_logic;
signal blit_dst_re : std_logic; signal blit_dst_re : std_logic;
signal blit_dst_be : unsigned(7 downto 0);
signal blit_dst_vld : std_logic; signal blit_dst_vld : std_logic;
signal blit_dst_cnt_x : unsigned(31 downto 0); signal blit_dst_cnt_x : unsigned(31 downto 0);
signal blit_dst_cnt_y : unsigned(31 downto 0); signal blit_dst_cnt_y : unsigned(31 downto 0);
@@ -258,38 +258,6 @@ architecture Behavioral of vga_frontend64 is
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin); type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
signal s, sn : vm_state_t; signal s, sn : vm_state_t;
type byte_en_rom_t is array (0 to 2*8-1) of unsigned (8-1 downto 0);
function gen_byte_en_rom(N : natural) return byte_en_rom_t is
variable k : integer;
variable result : byte_en_rom_t;
begin
k:=0;
result(k) := (others => '1');
k := k + 1;
for i in 1 to N-1 loop
result(k) := (N-1 downto i => '1') & (i-1 downto 0 => '0');
k := k + 1;
end loop;
result(k) := (others => '1');
k := k + 1;
for i in 1 to N-1 loop
result(k) := (N-1 downto i => '0') & (i-1 downto 0 => '1');
k := k + 1;
end loop;
return result;
end gen_byte_en_rom;
signal byte_en_rom : byte_en_rom_t := gen_byte_en_rom(8);
signal byte_en : unsigned (8-1 downto 0);
signal eb : std_logic;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
@@ -461,7 +429,7 @@ inst_bus_fifo: entity work.fifo_sync
bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
ADDR_O_scan; ADDR_O_scan;
bus_fifo_sel_in <= blit_dst_reg_be when CYC_O_blit_dst = '1' else (others => '1'); bus_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1');
bus_fifo_we_in <= CYC_O_blit_dst; bus_fifo_we_in <= CYC_O_blit_dst;
CYC_O <= bus_cycle_en; CYC_O <= bus_cycle_en;
@@ -663,8 +631,7 @@ inst_align_src : entity work.align
GENERIC MAP GENERIC MAP
( (
data_width => 64, data_width => 64,
aggregate_size => 8, aggregate_size => 8
allow_partial_valid => true
) )
PORT MAP PORT MAP
( (
@@ -673,12 +640,11 @@ inst_align_src : entity work.align
ce => blit_src_re, ce => blit_src_re,
eb => '1', eb => '1',
offset => blit_src_addr, offset => blit_src_addr,
din_last_vld => '0',
din_vld => blit_src_we, din_vld => blit_src_we,
din => MDAT_I, din => MDAT_I,
dout_vld => blit_src_reg_vld, dout_vld => blit_src_reg_vld,
dout => blit_src_reg, dout => blit_src_reg,
dout_be => blit_src_reg_be byte_en => open
); );
@@ -787,8 +753,7 @@ inst_align_dst : entity work.align
GENERIC MAP GENERIC MAP
( (
data_width => 64, data_width => 64,
aggregate_size => 8, aggregate_size => 8
allow_partial_valid => true
) )
PORT MAP PORT MAP
( (
@@ -797,24 +762,22 @@ inst_align_dst : entity work.align
eb => '1', eb => '1',
ce => blit_dst_re, ce => blit_dst_re,
offset => blit_addr_dst(2 downto 0), offset => blit_addr_dst(2 downto 0),
din_last_vld => '0',
din_vld => blit_dst_we, din_vld => blit_dst_we,
din => blitfifo_src_out, din => blitfifo_src_out,
dout_vld => blit_dst_reg_vld, dout_vld => blit_dst_reg_vld,
dout => blit_dst_reg, dout => blit_dst_reg,
dout_be => open byte_en => blit_dst_reg_be
); );
eb <= '1'; blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
blit_dst_reg_be <= byte_en_rom(to_integer(not eb & blit_addr_dst(2 downto 0))) when blit_dst_first = '1' else not blit_dst_reg_be when blit_dst_last = '1' else
not byte_en_rom(to_integer(not eb & blit_addr_dst(2 downto 0))) when blit_dst_last = '1' else (others => '1');
(others => '1');
blit_dst_we <= not blitfifo_src_empty; blit_dst_we <= not blitfifo_src_empty;
blit_dst_re <= CYC_O_blit_dst and bus_fifo_rdy and not blit_dst_last; blit_dst_re <= CYC_O_blit_dst and bus_fifo_rdy and not blit_dst_last;
blit_dst_vld <= blit_dst_reg_vld or blit_dst_last; blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
ADDR_O_blit_dst <= blit_addr_dst(31 downto 3) & "000" + blit_dst_offset; ADDR_O_blit_dst <= blit_addr_dst(31 downto 3) & "000" + blit_dst_offset;