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cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@914 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-05-15 16:00:13 +00:00
parent dff1254bd9
commit 66514fbf7c
3 changed files with 29 additions and 82 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/vga_frontend64.vhd
+12 -49
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@@ -186,7 +186,6 @@ architecture Behavioral of vga_frontend64 is
signal blit_src_addr : unsigned(2 downto 0);
signal blit_src_reg_vld : std_logic;
signal blit_src_reg : unsigned(63 downto 0);
signal blit_src_reg_be : unsigned(7 downto 0);
signal blit_src_rdy : std_logic;
signal blit_src_we : std_logic;
signal blit_src_re : std_logic;
@@ -218,6 +217,7 @@ architecture Behavioral of vga_frontend64 is
signal blit_dst_rdy : std_logic;
signal blit_dst_we : std_logic;
signal blit_dst_re : std_logic;
signal blit_dst_be : unsigned(7 downto 0);
signal blit_dst_vld : std_logic;
signal blit_dst_cnt_x : unsigned(31 downto 0);
signal blit_dst_cnt_y : unsigned(31 downto 0);
@@ -258,38 +258,6 @@ architecture Behavioral of vga_frontend64 is
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
signal s, sn : vm_state_t;
type byte_en_rom_t is array (0 to 2*8-1) of unsigned (8-1 downto 0);
function gen_byte_en_rom(N : natural) return byte_en_rom_t is
variable k : integer;
variable result : byte_en_rom_t;
begin
k:=0;
result(k) := (others => '1');
k := k + 1;
for i in 1 to N-1 loop
result(k) := (N-1 downto i => '1') & (i-1 downto 0 => '0');
k := k + 1;
end loop;
result(k) := (others => '1');
k := k + 1;
for i in 1 to N-1 loop
result(k) := (N-1 downto i => '0') & (i-1 downto 0 => '1');
k := k + 1;
end loop;
return result;
end gen_byte_en_rom;
signal byte_en_rom : byte_en_rom_t := gen_byte_en_rom(8);
signal byte_en : unsigned (8-1 downto 0);
signal eb : std_logic;
--------------------------------------------------------------------------
begin
@@ -461,7 +429,7 @@ inst_bus_fifo: entity work.fifo_sync
bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
ADDR_O_scan;
bus_fifo_sel_in <= blit_dst_reg_be when CYC_O_blit_dst = '1' else (others => '1');
bus_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1');
bus_fifo_we_in <= CYC_O_blit_dst;
CYC_O <= bus_cycle_en;
@@ -663,8 +631,7 @@ inst_align_src : entity work.align
GENERIC MAP
(
data_width => 64,
aggregate_size => 8,
allow_partial_valid => true
aggregate_size => 8
)
PORT MAP
(
@@ -673,12 +640,11 @@ inst_align_src : entity work.align
ce => blit_src_re,
eb => '1',
offset => blit_src_addr,
din_last_vld => '0',
din_vld => blit_src_we,
din => MDAT_I,
dout_vld => blit_src_reg_vld,
dout => blit_src_reg,
dout_be => blit_src_reg_be
byte_en => open
);
@@ -787,8 +753,7 @@ inst_align_dst : entity work.align
GENERIC MAP
(
data_width => 64,
aggregate_size => 8,
allow_partial_valid => true
aggregate_size => 8
)
PORT MAP
(
@@ -797,24 +762,22 @@ inst_align_dst : entity work.align
eb => '1',
ce => blit_dst_re,
offset => blit_addr_dst(2 downto 0),
din_last_vld => '0',
din_vld => blit_dst_we,
din => blitfifo_src_out,
dout_vld => blit_dst_reg_vld,
dout => blit_dst_reg,
dout_be => open
byte_en => blit_dst_reg_be
);
eb <= '1';
blit_dst_reg_be <= byte_en_rom(to_integer(not eb & blit_addr_dst(2 downto 0))) when blit_dst_first = '1' else
not byte_en_rom(to_integer(not eb & blit_addr_dst(2 downto 0))) when blit_dst_last = '1' else
(others => '1');
blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
not blit_dst_reg_be when blit_dst_last = '1' else
(others => '1');
blit_dst_we <= not blitfifo_src_empty;
blit_dst_re <= CYC_O_blit_dst and bus_fifo_rdy and not blit_dst_last;
blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
blit_dst_we <= not blitfifo_src_empty;
blit_dst_re <= CYC_O_blit_dst and bus_fifo_rdy and not blit_dst_last;
blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
---------------------------------------------------------------------------------
ADDR_O_blit_dst <= blit_addr_dst(31 downto 3) & "000" + blit_dst_offset;