diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt
index eb1489e..02dbb35 100644
--- a/lib/CPUs/MIPS/dist/tmpl/notes.txt
+++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt
@@ -3,13 +3,13 @@ Changes in release 12
 -----------------------------------------------------------------
 - reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked
   using a single mips*-elf-gcc command.
-  To use: Copy $THIS_REALEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/,
+  To use: Copy $THIS_RELEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/,
   and see bsp/examples/Makefile gcc usage
   GCC-provided crt*-functions are now called without problems.
   In summary: The toolchain is now more compliant to the intentional use of GCC.
 - mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O,
   which is now compliant to literature. 
-- gpio_wb.vhd: Timer reset is now removed. This helps to keep current time in case of CPU reset.
+- gpio_wb.vhd: Timer hard-reset is now removed. This helps to keep current time in case of CPU hard-reset.
 - new bsp-example source: gunzip
 - updated drawing 'mips_jbus_timing.pdf'
 - added drawing 'memory_map.pdf' 
@@ -26,17 +26,19 @@ Changes in release 12
 - bugfix: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
 - added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian)
 - Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
-- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of a MMU.
+- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU.
 - uart_wb.vhd: added interrupt enable
 - Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W. 
   Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant. 
-- added NMI pin (more MIPS compliant). Asserting causes exception. Exception vector is reset (0xBFC00000). 
-  Using NMI as reset is dangerous because periphery is not reseted. 
-  Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts) 
-- Bootloader: Startup now invalidates I/D-Caches at boot
+- added NMI/RST pin (more MIPS compliant). Transition Asserting/Deasserting causes exception. 
+  Exception vector is reset (0xBFC00000). It's a soft-reset, which can help debugging. NMI/RST is not maskable.
+  Using NMI/RST as reset is dangerous because periphery may not be reseted. Has to be done in S/W.
+  Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already.
+- Bootloader: Startup.S now invalidates I/D-Caches at boot.
+- uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge.
 - Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.
-  Newlib's memcpy() (MIPS-optimized) uses this for unaligned copy.  
-  Consectutive load instructions without nops using same target register (which is legal) like
+  Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug.  
+  Symptom: Consecutive load instructions without nops using same target register (which is legal) like
    lw $1, 0(mem)
    lwl $1, 1(mem)
   or
@@ -47,7 +49,7 @@ Changes in release 12
 -----------------------------------------------------------------
 Changes in release 11
 -----------------------------------------------------------------
-- bug-fix in mips_pipeline: pc_is_branch is now initialized at reset
+- bugfix in mips_pipeline: pc_is_branch is now initialized at reset
   (fixes CPU unrecoverable state after reset)
 - reverted "optimization" in mips_dcache, which behaved buggy during exceptions
 - new example source: test_exception
@@ -58,7 +60,7 @@ Changes in release 11
 -----------------------------------------------------------------
 Changes in release 10b
 -----------------------------------------------------------------
-- fixed compiler bug (missing nop after lw) in bootloader,
+- bugfix: fixed compiler bug (missing nop after lw) in bootloader,
   which caused exception during boot
 
 -----------------------------------------------------------------
@@ -68,13 +70,13 @@ async_port_wb:
 - added byte enable for async_port
 
 bootloader.c
-- fixed compiler bug (missing nop after lw)
+- bugfix: fixed compiler bug (missing nop after lw)
 
 mips-core
-- SEL_O lines are also asserted correctly during reads
+- bugfix: SEL_O lines are also asserted correctly during reads
 
 tools/romgen
-- TCL-Jtage now compatible with Chipscope 10.1
+- TCL-Jtag now compatible with Chipscope 10.1
 
 mips_sys.c
 - use byte enable for sram and flash