- added new FIFO generics

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git-svn-id: http://moon:8086/svn/vhdl/trunk@749 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/fifo_async.vhd

@@ -34,7 +34,10 @@ entity fifo_async is
 		addr_width			: natural := 4;
 		data_width			: natural := 8;
 		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4
+		almost_empty_thresh	: integer := 4;
+		allow_full_writes	: boolean := false;
+		allow_empty_reads	: boolean := false;
+		do_last_read_update	: boolean := true
 	);
 	Port
 	(
@@ -59,16 +62,21 @@ architecture Behavioral of fifo_async is
 	signal ptr_w		: unsigned (addr_width-1 downto 0);
 	signal ptr_r		: unsigned (addr_width-1 downto 0);
 	signal full			: std_logic;
+	signal empty		: std_logic;
 	signal pre_full		: STD_LOGIC;
 	signal pre_empty	: STD_LOGIC;
+	signal rinc			: std_logic;
 	
 begin
 
-	mem_wr_en	<= we and not full;
-	mem_rd_en	<= not pre_empty;
 	fifo_full	<= full;
+	fifo_empty	<= empty;
+	
+	mem_wr_en	<= (we and not full) when allow_full_writes = false else we;
+	rinc		<= (re and not empty) when allow_empty_reads = false else re;
+	mem_rd_en	<= not pre_empty when do_last_read_update = false else '1';
+	
 	
-	-- Instantiate the Unit Under Test (UUT)
 	inst_fifo_async_ctrl: entity work.fifo_async_ctrl
 	GENERIC MAP
 	(
@@ -81,12 +89,12 @@ begin
 		rst				=>	rst,
 		clk_w			=>	clk_w,
 		clk_r			=>	clk_r,
-		we				=>	we,
-		re				=>	re,
+		winc			=>	mem_wr_en,
+		rinc			=>	rinc,
 		ptr_w			=>	ptr_w,
 		ptr_r			=>	ptr_r,
 		fifo_full		=>	full,
-		fifo_empty		=>	fifo_empty,
+		fifo_empty		=>	empty,
 		fifo_pre_full	=>	pre_full,
 		fifo_pre_empty	=>	pre_empty,
 		fifo_afull		=>	fifo_afull,