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- added new FIFO generics

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git-svn-id: http://moon:8086/svn/vhdl/trunk@749 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-11 21:56:32 +00:00
parent 5889dc2d4a
commit 651cd11ec0
4 changed files with 50 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/FIFO/src/async_fifo_ctrl.vhd
+2 -5
View File
@@ -41,8 +41,8 @@ entity fifo_async_ctrl is
rst : in STD_LOGIC;
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
winc : in STD_LOGIC;
rinc : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_pre_full : out STD_LOGIC;
@@ -71,7 +71,6 @@ architecture Behavioral of fifo_async_ctrl is
signal pre_empty, pre_full : std_logic;
signal full, empty : std_logic;
signal winc, rinc : std_logic;
-- synthesis translate_off
signal diffw : signed (addr_width downto 0);
@@ -82,8 +81,6 @@ begin
ptr_w <= bcnt_w(addr_width-1 downto 0);
ptr_r <= bnxt_r(addr_width-1 downto 0);
winc <= we and (not full);
rinc <= re and (not empty);
fifo_full <= full;
fifo_empty <= empty;
fifo_pre_full <= pre_full;
lib/FIFO/src/fifo_async.vhd
+15 -7
View File
@@ -34,7 +34,10 @@ entity fifo_async is
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
);
Port
(
@@ -59,16 +62,21 @@ architecture Behavioral of fifo_async is
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : std_logic;
signal empty : std_logic;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
signal rinc : std_logic;
begin
mem_wr_en <= we and not full;
mem_rd_en <= not pre_empty;
fifo_full <= full;
fifo_empty <= empty;
mem_wr_en <= (we and not full) when allow_full_writes = false else we;
rinc <= (re and not empty) when allow_empty_reads = false else re;
mem_rd_en <= not pre_empty when do_last_read_update = false else '1';
-- Instantiate the Unit Under Test (UUT)
inst_fifo_async_ctrl: entity work.fifo_async_ctrl
GENERIC MAP
(
@@ -81,12 +89,12 @@ begin
rst => rst,
clk_w => clk_w,
clk_r => clk_r,
we => we,
re => re,
winc => mem_wr_en,
rinc => rinc,
ptr_w => ptr_w,
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => fifo_empty,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => fifo_afull,
lib/FIFO/src/fifo_sync.vhd
+18 -8
View File
@@ -34,7 +34,11 @@ entity fifo_sync is
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
);
Port
(
@@ -58,14 +62,20 @@ architecture Behavioral of fifo_sync is
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC;
signal empty : std_logic;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
signal rinc : std_logic;
begin
mem_wr_en <= not full;
mem_rd_en <= not pre_empty;
fifo_full <= full;
fifo_empty <= empty;
mem_wr_en <= (we and not full) when allow_full_writes = false else we;
rinc <= (re and not empty) when allow_empty_reads = false else re;
mem_rd_en <= not pre_empty when do_last_read_update = false else '1';
inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
GENERIC MAP
@@ -78,12 +88,12 @@ inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
(
rst => rst,
clk => clk,
we => we,
re => re,
winc => mem_wr_en,
rinc => rinc,
ptr_w => ptr_w,
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => fifo_empty,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => fifo_afull,
@@ -100,9 +110,9 @@ inst_dpram_1w1r: entity work.dpram_1w1r
PORT MAP(
clka => clk,
clkb => clk,
en_a => mem_wr_en,
en_a => '1',
en_b => mem_rd_en,
we_a => we,
we_a => mem_wr_en,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => data_w,
lib/FIFO/src/sync_fifo_ctrl.vhd
+15 -19
View File
@@ -37,8 +37,8 @@ entity fifo_sync_ctrl is
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
winc : in STD_LOGIC;
rinc : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_pre_full : out STD_LOGIC;
@@ -57,14 +57,10 @@ architecture Behavioral of fifo_sync_ctrl is
signal empty, full : std_logic;
signal pre_empty, pre_full : std_logic;
signal was_write : std_logic;
signal write, read : std_logic;
signal diff : unsigned (addr_width downto 0);
begin
read <= re and not empty;
write <= we and not full;
fifo_full <= full;
fifo_empty <= empty;
fifo_pre_full <= pre_full;
@@ -77,9 +73,9 @@ proc_diff_gen:
if rst = '1' then
diff <= (others => '0');
elsif rising_edge(clk) then
if write = '1' and read = '0' then
if winc = '1' and rinc = '0' then
diff <= diff + 1;
elsif write = '0' and read = '1' then
elsif winc = '0' and rinc = '1' then
diff <= diff - 1;
end if;
end if;
@@ -134,14 +130,14 @@ proc_empty_reg:
end process;
proc_status_w:
process(was_write, pW_next, pR_next, pW, pR, write, read)
process(was_write, pW_next, pR_next, pW, pR, winc, rinc)
begin
if (pW_next = pR) and (write = '1' or was_write = '1') then
if (pW_next = pR) and (winc = '1' or was_write = '1') then
pre_full <= '1';
else
pre_full <= '0';
end if;
if (pR_next = pW) and (read = '1' or was_write = '0') then
if (pR_next = pW) and (rinc = '1' or was_write = '0') then
pre_empty <= '1';
else
pre_empty <= '0';
@@ -154,45 +150,45 @@ proc_flag_write:
if rst = '1' then
was_write <= '0';
elsif rising_edge(clk) then
if write = '1' then
if winc = '1' then
was_write <= '1';
elsif read = '1' then
elsif rinc = '1' then
was_write <= '0';
end if;
end if;
end process;
proc_ptr_w:
process(rst, clk, pW, write)
process(rst, clk, pW, winc)
begin
if rst = '1' then
pW <= to_unsigned(0, addr_width);
pW_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if write = '1' then
if winc = '1' then
pW <= pW_next;
end if;
end if;
pW_next <= pW;
if write = '1' then
if winc = '1' then
pW_next <= pW + 1;
end if;
ptr_w <= pW;
end process;
proc_ptr_r:
process(rst, clk, pR_next, pR, read)
process(rst, clk, pR_next, pR, rinc)
begin
if rst = '1' then
pR <= to_unsigned(0, addr_width);
pR_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if read = '1' then
if rinc = '1' then
pR <= pR_next;
end if;
end if;
pR_next <= pR;
if read = '1' then
if rinc = '1' then
pR_next <= pR + 1;
end if;
ptr_r <= pR_next;