From 6409d43d38ef224df392dcb4b2abd34fd309a050 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 18 Mar 2010 20:18:25 +0000
Subject: [PATCH] - added integer shift amount (sa)  with positive value for
 left shift and negaitve values for right shift - removed shift_left port
 Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to
 CVS Suite for more features and support: http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@799 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/emac/src/shifter.vhd | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/lib/emac/src/shifter.vhd b/lib/emac/src/shifter.vhd
index b0d09d2..e988e63 100644
--- a/lib/emac/src/shifter.vhd
+++ b/lib/emac/src/shifter.vhd
@@ -16,8 +16,7 @@ ENTITY shifter IS
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
-		shift_left	: in  STD_LOGIC;
-		sa			: in  unsigned(NextExpBaseTwo(data_width/aggregate_size)-1 downto 0);
+		sa			: in  integer;
 		din_vld		: in  STD_LOGIC;
 		din			: in  unsigned(data_width-1 downto 0);
 		dout_vld	: out STD_LOGIC;
@@ -29,29 +28,29 @@ END shifter;
 ARCHITECTURE behavior OF shifter IS
 
 	constant num_rounds	: natural := NextExpBaseTwo(data_width/aggregate_size);
+	subtype sa_rnd_t is signed(num_rounds-1 downto 0);
 	subtype word_t is unsigned(data_width-1 downto 0);
 	type word_array_t is array (0 to num_rounds) of word_t;
 
 	signal rot_data			: word_array_t;
-	signal sa_rnd			: unsigned (num_rounds-1 downto 0);
+	signal sa_rnd			: sa_rnd_t;
 
-	subtype sa_rnd_t is unsigned(num_rounds-1 downto 0);
 	type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
 	signal sa_rnd_pipe		: sa_rnd_array_t;
 	signal dout_vld_pipe	: unsigned(0 to num_rounds);
 	
 --------------------------------------------------------------------------
-function rot_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
+function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
 	variable result : unsigned(x'range);
 	constant sa : natural := (2**stage_num) * size;
 	begin
 	if en = '1' then
-		result := x(sa-1 downto 0) & x(x'left downto sa);
+		result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
 	else
 		result := x;
 	end if;	
 	return result;
-end rot_stage;
+end rol_stage;
 
 --------------------------------------------------------------------------
 begin
@@ -66,10 +65,10 @@ begin
 gen_rotate_right:
 	for stage in 0 to num_rounds-1 generate
 	begin
-		rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
+		rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
 	end generate;
 	
-	sa_rnd			<= not sa + 1 when shift_left = '1' else sa;
+	sa_rnd			<= to_signed(sa, num_rounds);
 	dout			<= rot_data(num_rounds);
 	dout_vld		<= din_vld;
 	
@@ -81,7 +80,7 @@ if do_pipelined = true generate
 begin
 	
 	rot_data(0)			<= din;
-	sa_rnd_pipe(0)		<= not sa + 1 when shift_left = '1' else sa;
+	sa_rnd_pipe(0)		<= to_signed(sa, num_rounds);
 	dout_vld_pipe(0)	<= din_vld;
 	
 gen_rotate_right:
@@ -96,7 +95,7 @@ gen_rotate_right:
 					dout_vld_pipe(stage+1)	<= dout_vld_pipe(stage);
 					if dout_vld_pipe(stage) = '1' then
 						sa_rnd_pipe(stage+1)	<= sa_rnd_pipe(stage);
-						rot_data(stage+1)		<= rot_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
+						rot_data(stage+1)		<= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
 					end if;
 				end if;
 			end if;