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- simplified clock stuff

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1165 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 08:30:01 +00:00
parent 752b788327
commit 628593a879
2 changed files with 47 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys_sim.vhd
+21 -10
View File
@@ -810,24 +810,35 @@ inst_ssram_port_wb : entity work.ssram_port_wb
ssram_bw_n => sys_ssram_bw_n ssram_bw_n => sys_ssram_bw_n
); );
inst_sys_clock : entity work.sys_clock inst_clockgen_cpu : entity work.clockgen
GENERIC MAP GENERIC MAP
( (
clk_in_freq => sys_freq_in, clk_in_freq => sys_freq_in,
cpu_clk_out_freq => cpu_freq, clk_out_freq => cpu_freq
vga_clk_out_freq => vga_freq
) )
PORT MAP PORT MAP
( (
-- Clocks and Reset -- Clocks and Reset
rst_in => rst_in, -- external async reset, low active rst_in => rst_in,
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board clk_in => sys_clk_in,
cpu_clk_out => CLK_O, clk_out => CLK_O,
cpu_rst_out => RST_O, rst_out => RST_O
vga_clk_out => vga_clk,
vga_rst_out => vga_rst
); );
inst_clocken_vga : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
clk_out_freq => vga_freq
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in,
clk_in => sys_clk_in,
clk_out => vga_clk,
rst_out => vga_rst
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP GENERIC MAP
projects/mips_sys/src/sys_clock.vhd
+26 -88
View File
@@ -30,35 +30,28 @@ USE WORK.utils_pkg.ALL;
Library UNISIM; Library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
entity sys_clock is entity clockgen is
generic generic
( (
clk_in_freq : real := 100.0; clk_in_freq : real := 100.0;
cpu_clk_out_freq : real := 100.0; clk_out_freq : real := 100.0
vga_clk_out_freq : real := 100.0
); );
port port
( (
-- Clocks and Reset -- Clocks and Reset
rst_in : in std_logic; -- external async reset, low active rst_in : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
cpu_clk_out : out std_logic; clk_out : out std_logic;
cpu_rst_out : out std_logic; rst_out : out std_logic
vga_clk_out : out std_logic;
vga_rst_out : out std_logic
); );
end; end;
architecture tech of sys_clock is architecture tech of clockgen is
signal vga_clk0 : std_logic; signal clk0 : std_logic;
signal vga_clkfx : std_logic; signal clk0_bufg : std_logic;
signal vga_clk0_bufg : std_logic; signal clkfx : std_logic;
signal cpu_clk0 : std_logic; signal fx_lock : std_logic;
signal cpu_clk0_bufg : std_logic;
signal cpu_clkfx : std_logic;
signal vga_fx_lock : std_logic;
signal cpu_fx_lock : std_logic;
begin begin
@@ -66,15 +59,14 @@ begin
------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------
-- Clock generation -- Clock generation
------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------
-- Compnent instantiation inst_DCM_FX : DCM_BASE
inst_DCM_VGA_FX : DCM_BASE
generic map generic map
( (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32 CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32 CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
@@ -91,92 +83,38 @@ begin
) )
port map port map
( (
CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D) CLKFX => clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => vga_fx_lock, -- DCM LOCK status output LOCKED => fx_lock, -- DCM LOCK status output
CLKFB => vga_clk0_bufg, -- DCM clock feedback CLKFB => clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => rst_in -- DCM asynchronous reset input RST => rst_in -- DCM asynchronous reset input
); );
BUFG_vga_clk0 : BUFG BUFG_clk0 : BUFG
port map port map
( (
O => vga_clk0_bufg, -- Clock buffer output O => clk0_bufg, -- Clock buffer output
I => vga_clk0 -- Clock buffer input I => clk0 -- Clock buffer input
); );
-- Compnent instantiation clk_out <= clkfx;
inst_DCM_CPU_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => cpu_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => cpu_fx_lock, -- DCM LOCK status output
CLKFB => cpu_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => rst_in -- DCM asynchronous reset input
);
BUFG_cpu_clk0 : BUFG rst_out_reg:
port map process(clkfx)
(
O => cpu_clk0_bufg, -- Clock buffer output
I => cpu_clk0 -- Clock buffer input
);
vga_clk_out <= vga_clkfx;
cpu_clk_out <= cpu_clkfx;
cpu_rst_out_reg:
process(cpu_clkfx)
begin begin
if rising_edge(cpu_clkfx) then if rising_edge(clkfx) then
cpu_rst_out <= not cpu_fx_lock; rst_out <= not fx_lock;
end if; end if;
end process; end process;
vga_rst_out_reg:
process(vga_clkfx)
begin
if rising_edge(vga_clkfx) then
vga_rst_out <= not vga_fx_lock;
end if;
end process;
end architecture tech; end architecture tech;