diff --git a/lib/emac/sim/tb_emac_top_jb.fdo b/lib/emac/sim/tb_emac_top_jb.fdo index dd1a10c..aa5fae4 100644 --- a/lib/emac/sim/tb_emac_top_jb.fdo +++ b/lib/emac/sim/tb_emac_top_jb.fdo @@ -13,6 +13,9 @@ vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd" vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" +vcom -explicit -93 "../../JBUS/src/busmaster_types.vhd" +vcom -explicit -93 "../../JBUS/src/busmaster_sync.vhd" +vcom -explicit -93 "../../JBUS/src/dmac.vhd" vcom -explicit -93 "../src/piso.vhd" vcom -explicit -93 "../src/sipo.vhd" vcom -explicit -93 "../src/crc32.vhd" @@ -28,4 +31,4 @@ do {tb_emac_top_jb.wdo} view structure view signals -run 50000 us +run 16000 us diff --git a/lib/emac/sim/tb_emac_top_jb.wdo b/lib/emac/sim/tb_emac_top_jb.wdo index 30d062e..a9563ac 100644 --- a/lib/emac/sim/tb_emac_top_jb.wdo +++ b/lib/emac/sim/tb_emac_top_jb.wdo @@ -3,6 +3,8 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate -divider {Ethernet MAC} add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i +add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/ram64 +add wave -noupdate -divider Slave add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i @@ -14,6 +16,18 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o +add wave -noupdate -divider Master +add wave -noupdate -format Logic /tb_emac_top_jb/cyc_o +add wave -noupdate -format Logic /tb_emac_top_jb/stb_o +add wave -noupdate -format Logic /tb_emac_top_jb/we_o +add wave -noupdate -format Literal /tb_emac_top_jb/sel_o +add wave -noupdate -format Logic /tb_emac_top_jb/ack_i +add wave -noupdate -format Logic /tb_emac_top_jb/mrdy_o +add wave -noupdate -format Logic /tb_emac_top_jb/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/addr_o +add wave -noupdate -format Literal /tb_emac_top_jb/mdat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/mdat_o +add wave -noupdate -divider MII add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er @@ -53,6 +67,21 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en +add wave -noupdate -divider RX-DMA +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_req +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_gnt +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_start +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_active +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_end +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rdy +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_en +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rw +add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_start +add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_num_xfers +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_auto_inc +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete_ack +add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/s add wave -noupdate -divider RX add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst @@ -190,7 +219,7 @@ add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {242561800 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {10461869973 ps} 0} {{Cursor 5} {4181100 ps} 0} +WaveRestoreCursors {{Cursor 1} {15999470765 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {10461803096 ps} 0} {{Cursor 5} {10000 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -204,4 +233,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {10461583799 ps} {10462629245 ps} +WaveRestoreZoom {0 ps} {379173 ps} diff --git a/lib/emac/src/emac_top_jb.vhd b/lib/emac/src/emac_top_jb.vhd index cf7c2ec..7a84e8e 100644 --- a/lib/emac/src/emac_top_jb.vhd +++ b/lib/emac/src/emac_top_jb.vhd @@ -5,6 +5,7 @@ use std.textio.all; -- Imports the standard textio package. use work.emac_types.all; use work.utils_pkg.all; +use work.busmaster_types.all; ENTITY emac_top_jb IS Generic @@ -15,6 +16,7 @@ ENTITY emac_top_jb IS ); Port ( + -- JBUS Slave CLK_I : in STD_LOGIC; RST_I : in STD_LOGIC; INT_O : out STD_LOGIC; @@ -28,6 +30,20 @@ ENTITY emac_top_jb IS ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); + + -- JBUS Master + ACK_I : in std_logic; + SRDY_I : in std_logic; + MDAT_I : in unsigned(31 downto 0); + MDAT_O : out unsigned(31 downto 0); + ADDR_O : out unsigned(31 downto 0); + SEL_O : out unsigned(3 downto 0); + WE_O : out std_logic; + CYC_O : out std_logic; + STB_O : out std_logic; + MRDY_O : out std_logic; + + -- MII mii_rx_clk : in STD_LOGIC; mii_rx_dv : in STD_LOGIC; mii_rx_er : in STD_LOGIC; @@ -45,6 +61,12 @@ END emac_top_jb; ARCHITECTURE behavior OF emac_top_jb IS + -- Constants + constant DMA_NUM_CHANNEL : integer := 2; + constant DMA_CH_WRITE : integer := 0; + constant DMA_CH_READ : integer := 1; + constant DMA_RW_CONF : unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01"; + -- Signals for EMAC connections signal tx_ctrl_in : tx_ctrl_in_t; signal tx_ctrl_out : tx_ctrl_out_t; @@ -66,13 +88,55 @@ ARCHITECTURE behavior OF emac_top_jb IS signal read : std_logic; signal write : std_logic; - signal data_read : std_logic; - signal data_write : std_logic; + signal rx_read_en_CPU : std_logic; + signal rx_req_en_CPU : std_logic; + signal rx_free_en_CPU : std_logic; + signal tx_write_en_CPU : std_logic; signal reg_read : std_logic; signal reg_write : std_logic; signal reg_addr : unsigned(3 downto 0); + -- DMA Controller + signal dma_master_req : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_master_gnt : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); + signal dma_req_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_req_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); + signal dma_req_addr_auto_inc : unsigned(DMA_NUM_CHANNEL-1 downto 0); + type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0); + signal dma_req_addr : array32_t; + signal dma_req_num_xfers : array32_t; + + signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); + + signal dma_start : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_active : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_end : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); + signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0); + signal dma_bus_cmd_we : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); + type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t; + signal dma_bus_cmd : array_bus_cmd_t; + + -- Busmaster arbiter + signal arb_idx : natural range 0 to DMA_NUM_CHANNEL-1; + + -- BUS Master controller + signal bus_din_re : std_logic; + signal bus_cmd_cycle_finished : std_logic; + signal bus_cmd_cycle_en : std_logic := '0'; + signal bus_cmd_rdy : std_logic; + signal bus_cmd_we : std_logic := '0'; + signal bus_cmd : bm_cmd_t; + signal bus_din_rdy : std_logic; + signal bus_din_vld : std_logic := '0'; + signal bus_din : unsigned(31 downto 0) := (others => '-'); + signal bus_dout : unsigned(31 downto 0); + signal bus_dout_vld : std_logic; + signal bus_dout_re : std_logic := '0'; + begin mii_gtx_clk <= '0'; @@ -80,18 +144,29 @@ begin SRDY_O <= CYC_I and ready; read <= STB_I and CYC_I and not WE_I; write <= STB_I and CYC_I and WE_I; - data_read <= read and ADDR_I(15); - data_write <= write and ADDR_I(15); + rx_read_en_CPU <= read and ADDR_I(15); + tx_write_en_CPU <= write and ADDR_I(15); reg_read <= read and not ADDR_I(15); reg_write <= write and not ADDR_I(15); reg_addr <= ADDR_I(5 downto 2); ready <= not tx_ctrl_in.pkt_alloc_en; - tx_din_vld <= data_write; + tx_din_vld <= tx_write_en_CPU; tx_din <= DAT_I; - rx_dout_re <= data_read; + rx_ctrl_in.pkt_free_en <= rx_free_en_CPU or dma_end(0); + rx_ctrl_in.pkt_req_en <= rx_req_en_CPU or dma_start(0); + + rx_dout_re <= rx_read_en_CPU or (dma_active(DMA_CH_WRITE) and bus_din_rdy); + + bus_din <= rx_dout; + bus_din_vld <= dma_active(DMA_CH_WRITE); + dma_master_gnt(0) <= SRDY_I; + dma_req_en(0) <= rx_ctrl_out.pkt_avail; + dma_req_num_xfers(0) <= X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) when rx_ctrl_out.rx_size(1 downto 0) = "00" else X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) + 1; + dma_req_addr(0) <= X"00000800"; + dma_req_addr_auto_inc <= "11"; ------------------------------------------------------------------ registers_write: @@ -101,8 +176,8 @@ registers_write: tx_ctrl_in.pkt_alloc_en <= '0'; tx_ctrl_in.pkt_commit_en <= '0'; tx_ctrl_in.reset <= '0'; - rx_ctrl_in.pkt_free_en <= '0'; - rx_ctrl_in.pkt_req_en <= '0'; + rx_free_en_CPU <= '0'; + rx_req_en_CPU <= '0'; rx_ctrl_in.reset <= '0'; if RST_I = '1' then rx_int_en <= '0'; @@ -125,8 +200,8 @@ registers_write: rx_ctrl_in.Gbps_en <= DAT_I(30); rx_ctrl_in.fcs_chk_en <= DAT_I(29); rx_ctrl_in.promiscious <= DAT_I(23); - rx_ctrl_in.pkt_req_en <= DAT_I(17); - rx_ctrl_in.pkt_free_en <= DAT_I(16); + rx_req_en_CPU <= DAT_I(17); + rx_free_en_CPU <= DAT_I(16); rx_int_en <= DAT_I(4); -- 0x0004 @@ -177,7 +252,7 @@ registers_read: process(CLK_I) begin if rising_edge(CLK_I) then - ACK_O <= data_read; + ACK_O <= rx_read_en_CPU; DAT_O <= rx_dout; if reg_read = '1' then @@ -301,5 +376,128 @@ inst_emac_tx : entity work.emac_tx ); +gen_dmac: +for i in 0 to DMA_NUM_CHANNEL-1 generate + + dma_bus_cmd_cycle_finished(i) <= bus_cmd_cycle_finished; + dma_bus_cmd_rdy(i) <= bus_cmd_rdy; + + inst_dmac : entity work.dmac + Generic map + ( + DATA_WIDTH => 32, + XFER_CHUNK_SIZE => 32 + ) + Port map + ( + clk => CLK_I, + rst => RST_I, + + master_req => dma_master_req(i), + master_gnt => dma_master_gnt(i), + + req_rdy => dma_req_rdy(i), + req_en => dma_req_en(i), + req_rw => DMA_RW_CONF(i), + req_addr_auto_inc => dma_req_addr_auto_inc(i), + req_addr_start => dma_req_addr(i), + req_num_xfers => dma_req_num_xfers(i), + + req_complete => dma_req_complete(i), + req_complete_ack => dma_req_complete_ack(i), + + dma_start => dma_start(i), + dma_active => dma_active(i), + dma_end => dma_end(i), + + -- busmaster control + bus_cyc_complete => dma_bus_cmd_cycle_finished(i), + bus_cmd_rdy => dma_bus_cmd_rdy(i), + bus_cmd_we => dma_bus_cmd_we(i), + bus_cmd_cycle_en => dma_bus_cmd_cycle_en(i), + + -- busmaster command + bus_cmd_out => dma_bus_cmd(i) + ); + +end generate; + +inst_busmaster_sync : entity work.busmaster_sync + GENERIC MAP + ( + DATA_WIDTH => 32, + FIFO_DEPTH => 4 + ) + PORT MAP + ( + -- System signals + rst => RST_I, + clk => CLK_I, + + cmd_cycle_finished => bus_cmd_cycle_finished, + cmd_cycle_en => bus_cmd_cycle_en, + + cmd_rdy => bus_cmd_rdy, + cmd_we => bus_cmd_we, + cmd_in => bus_cmd, + + din_rdy => bus_din_rdy, + din_we => bus_din_vld, + din => bus_din, + + dout => bus_dout, + dout_vld => bus_dout_vld, + dout_re => bus_dout_re, + + -- JBUS Master signals + CYC_O => CYC_O, + STB_O => STB_O, + WE_O => WE_O, + SEL_O => SEL_O, + ACK_I => ACK_I, + SRDY_I => SRDY_I, + MRDY_O => MRDY_O, + ADDR_O => ADDR_O, + MDAT_I => MDAT_I, + MDAT_O => MDAT_O + ); + +arbiter_proc: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + dma_master_gnt <= (others => '0'); + arb_idx <= 0; + elsif dma_master_req(arb_idx) = '0' then + if arb_idx /= DMA_NUM_CHANNEL-1 then + arb_idx <= arb_idx + 1; + else + arb_idx <= 0; + end if; + else + dma_master_gnt <= (others => '0'); + dma_master_gnt(arb_idx) <= '1'; + end if; + end if; + end process; + +arbiter_mux: + process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en) + variable v_bus_cmd_we : std_logic; + variable v_bus_cmd_cycle_en : std_logic; + begin + v_bus_cmd_we := '0'; + v_bus_cmd_cycle_en := '0'; + for i in 0 to DMA_NUM_CHANNEL-1 loop + v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i); + v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i); + if dma_master_gnt(i) = '1' then + bus_cmd <= dma_bus_cmd(i); + end if; + end loop; + bus_cmd_we <= v_bus_cmd_we; + bus_cmd_cycle_en <= v_bus_cmd_cycle_en; +end process; end behavior; diff --git a/lib/emac/src/tb_emac_top_jb.vhd b/lib/emac/src/tb_emac_top_jb.vhd index b32ae9c..41c91b5 100644 --- a/lib/emac/src/tb_emac_top_jb.vhd +++ b/lib/emac/src/tb_emac_top_jb.vhd @@ -53,6 +53,18 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS signal status_reg : unsigned(31 downto 0) := (others => '0'); signal size_reg : unsigned(31 downto 0) := (others => '0'); + -- Master + signal CYC_O : std_logic; + signal STB_O : std_logic; + signal WE_O : std_logic; + signal SEL_O : unsigned(3 downto 0) := (others => '1'); + signal ACK_I : std_logic := '0'; + signal MRDY_O : std_logic := '1'; + signal SRDY_I : std_logic := '1'; + signal ADDR_O : unsigned(31 downto 0) := (others => '-'); + signal MDAT_I : unsigned(31 downto 0) := (others => '-'); + signal MDAT_O : unsigned(31 downto 0) := (others => '-'); + -- MII signals signal mii_rx_clk_board : std_logic := '1'; signal mii_tx_clk_board : std_logic := '1'; @@ -90,8 +102,86 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C"; constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_8000"; + + -- 64Bit RAM + signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-'); + signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-'); + + type ram_t is array (0 to 511) of unsigned(63 downto 0); + + signal ram64 : ram_t; + + BEGIN + MDAT_I <= MDAT_I_64(31 downto 0); + MDAT_O_64 <= MDAT_O & MDAT_O; + + process(CLK) + variable res: unsigned(63 downto 0); + variable ram_data : unsigned(63 downto 0); + variable data8: unsigned(7 downto 0); + begin + if rising_edge(CLK) then + if RST = '1' then + data8 := X"00"; + for i in 0 to 255 loop + ram_data(7 downto 0) := data8; + data8 := data8 + 1; + ram_data(15 downto 8) := data8; + data8 := data8 + 1; + ram_data(23 downto 16) := data8; + data8 := data8 + 1; + ram_data(31 downto 24) := data8; + data8 := data8 + 1; + ram_data(39 downto 32) := data8; + data8 := data8 + 1; + ram_data(47 downto 40) := data8; + data8 := data8 + 1; + ram_data(55 downto 48) := data8; + data8 := data8 + 1; + ram_data(63 downto 56) := data8; + data8 := data8 + 1; + ram64(i) <= ram_data; + end loop; + else + ACK_I <= '0'; + if (CYC_O and STB_O) = '1' then + if WE_O = '0' then + ACK_I <= '1'; + ram_data := ram64(to_integer(ADDR_O(31 downto 3))); + if ADDR_O(2) = '0' then + res := ram_data; + else + res := ram_data(31 downto 0) & ram_data(63 downto 32); + end if; + else -- WE=1 + ram_data := ram64(to_integer(ADDR_O(31 downto 3))); + -- ram_data := (others => '-'); + if ADDR_O(2) = '0' then + if SEL_O = "11111111" then + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64; + elsif SEL_O = "00001111" then + ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0); + elsif SEL_O = "11110000" then + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0); + end if; + else + if SEL_O = "11111111" then + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32); + elsif SEL_O = "00001111" then + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0); + elsif SEL_O = "11110000" then + ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32); + end if; + end if; + end if; + end if; + MDAT_I_64 <= res; + end if; + end if; + end process; + inst_emac_top_jb : entity work.emac_top_jb GENERIC MAP ( @@ -101,6 +191,7 @@ inst_emac_top_jb : entity work.emac_top_jb ) PORT MAP ( + -- JBUS Slave signals CLK_I => CLK, RST_I => RST, INT_O => INT_O, @@ -114,6 +205,19 @@ inst_emac_top_jb : entity work.emac_top_jb ADDR_I => ADDR_I, DAT_I => DAT_I, DAT_O => DAT_O, + + -- JBUS Master signals + CYC_O => CYC_O, + STB_O => STB_O, + WE_O => WE_O, + SEL_O => SEL_O, + ACK_I => ACK_I, + SRDY_I => SRDY_I, + MRDY_O => MRDY_O, + ADDR_O => ADDR_O, + MDAT_I => MDAT_I, + MDAT_O => MDAT_O, + mii_rx_clk => mii_rx_clk_board, mii_rx_dv => mii_rx_dv, mii_rx_er => mii_rx_er, @@ -388,6 +492,7 @@ STIMULUS: process variable size, num_words : natural; begin + return; emac_action <= emac_wait_data; -- check if data available @@ -473,6 +578,7 @@ STIMULUS: process procedure emac_free is begin + return; -- RX- DEALLOCATION emac_action <= emac_free;