From 61d9104fb22f48a1c0d96b170e7511ad910fec0e Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 9 Feb 2013 09:27:21 +0000 Subject: [PATCH] Initial revision Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@943 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/rams/dpram_1w1r2c_ra_sim.vhd | 82 +++++++++++++++++++++++++++ lib/rams/dpram_1w1r2c_ra_xil.vhd | 82 +++++++++++++++++++++++++++ lib/rams/dpram_1w1r2c_ro_sim.vhd | 80 +++++++++++++++++++++++++++ lib/rams/dpram_1w1r2c_ro_xil.vhd | 81 +++++++++++++++++++++++++++ lib/rams/dpram_2w2r2c_ra_sim.vhd | 95 ++++++++++++++++++++++++++++++++ lib/rams/dpram_2w2r2c_ra_xil.vhd | 93 +++++++++++++++++++++++++++++++ lib/rams/dpram_2w2r2c_ro_sim.vhd | 88 +++++++++++++++++++++++++++++ lib/rams/dpram_2w2r2c_ro_xil.vhd | 88 +++++++++++++++++++++++++++++ 8 files changed, 689 insertions(+) create mode 100644 lib/rams/dpram_1w1r2c_ra_sim.vhd create mode 100644 lib/rams/dpram_1w1r2c_ra_xil.vhd create mode 100644 lib/rams/dpram_1w1r2c_ro_sim.vhd create mode 100644 lib/rams/dpram_1w1r2c_ro_xil.vhd create mode 100644 lib/rams/dpram_2w2r2c_ra_sim.vhd create mode 100644 lib/rams/dpram_2w2r2c_ra_xil.vhd create mode 100644 lib/rams/dpram_2w2r2c_ro_sim.vhd create mode 100644 lib/rams/dpram_2w2r2c_ro_xil.vhd diff --git a/lib/rams/dpram_1w1r2c_ra_sim.vhd b/lib/rams/dpram_1w1r2c_ra_sim.vhd new file mode 100644 index 0000000..7b44736 --- /dev/null +++ b/lib/rams/dpram_1w1r2c_ra_sim.vhd @@ -0,0 +1,82 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity dpram_1w1r2c_ra is + Generic ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_1w1r2c_ra; + +architecture Behavioral of dpram_1w1r2c_ra is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + signal RAM : RAMtype; + signal addr_b_r : unsigned (addr_width-1 downto 0); + +begin + + dout_b <= RAM(to_integer(addr_b_r)); + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; + end if; + end if; +end if; +end process; + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + addr_b_r <= addr_b; + end if; +end if; +end process; + + +end Behavioral; + diff --git a/lib/rams/dpram_1w1r2c_ra_xil.vhd b/lib/rams/dpram_1w1r2c_ra_xil.vhd new file mode 100644 index 0000000..8c0b54b --- /dev/null +++ b/lib/rams/dpram_1w1r2c_ra_xil.vhd @@ -0,0 +1,82 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity dpram_1w1r2c_ra is + Generic ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_1w1r2c_ra; + +architecture Behavioral of dpram_1w1r2c_ra is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + signal RAM : RAMtype; + signal addr_b_r : unsigned (addr_width-1 downto 0); + +begin + + dout_b <= RAM(to_integer(addr_b_r)); + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; + end if; + end if; +end if; +end process; + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + addr_b_r <= addr_b; + end if; +end if; +end process; + + +end Behavioral; + diff --git a/lib/rams/dpram_1w1r2c_ro_sim.vhd b/lib/rams/dpram_1w1r2c_ro_sim.vhd new file mode 100644 index 0000000..d549f16 --- /dev/null +++ b/lib/rams/dpram_1w1r2c_ro_sim.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity dpram_1w1r2c_ro is + Generic ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_1w1r2c_ro; + +architecture Behavioral of dpram_1w1r2c_ro is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + signal RAM : RAMtype; + +begin + + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; + end if; + end if; +end if; +end process; + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + dout_b <= RAM(to_integer(addr_b)); + end if; +end if; +end process; + + +end Behavioral; + diff --git a/lib/rams/dpram_1w1r2c_ro_xil.vhd b/lib/rams/dpram_1w1r2c_ro_xil.vhd new file mode 100644 index 0000000..32e4b42 --- /dev/null +++ b/lib/rams/dpram_1w1r2c_ro_xil.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity dpram_1w1r2c_ro is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_1w1r2c_ro; + +architecture Behavioral of dpram_1w1r2c_ro is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + signal RAM : RAMtype; + +begin + +process (clk_a) + begin + if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; + end if; + end if; + end if; +end process; + +process (clk_b) + begin + if clk_b'event and clk_b = '1' then + if en_b = '1' then + dout_b <= RAM(to_integer(addr_b)); + end if; + end if; +end process; + + +end Behavioral; + diff --git a/lib/rams/dpram_2w2r2c_ra_sim.vhd b/lib/rams/dpram_2w2r2c_ra_sim.vhd new file mode 100644 index 0000000..1d860c7 --- /dev/null +++ b/lib/rams/dpram_2w2r2c_ra_sim.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity dpram_2w2r2c_ra is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + we_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + din_b : in unsigned (data_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_2w2r2c_ra; + +architecture Behavioral of dpram_2w2r2c_ra is + + constant depth : integer := 2**addr_width; + signal addr_a_r : unsigned (addr_width-1 downto 0); + signal addr_b_r : unsigned (addr_width-1 downto 0); + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + signal RAM : RAMtype; + +begin + + dout_a <= RAM(to_integer(addr_a_r)); + dout_b <= RAM(to_integer(addr_b_r)); + +process (clk_a, clk_b) +begin + if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; + elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then + RAM(to_integer(addr_b)) <= din_b; + end if; +end process; + +process (clk_a) +begin + if clk_a'event and clk_a = '1' then + if en_a = '1' then + addr_a_r <= addr_a; + end if; + end if; +end process; + +process (clk_b) +begin + if clk_b'event and clk_b = '1' then + if en_b = '1' then + addr_b_r <= addr_b; + end if; + end if; +end process; + +end Behavioral; + diff --git a/lib/rams/dpram_2w2r2c_ra_xil.vhd b/lib/rams/dpram_2w2r2c_ra_xil.vhd new file mode 100644 index 0000000..8847b0b --- /dev/null +++ b/lib/rams/dpram_2w2r2c_ra_xil.vhd @@ -0,0 +1,93 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity dpram_2w2r2c_ra is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + we_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + din_b : in unsigned (data_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_2w2r2c_ra; + +architecture Behavioral of dpram_2w2r2c_ra is + + constant depth : integer := 2**addr_width; + signal addr_a_r : unsigned (addr_width-1 downto 0); + signal addr_b_r : unsigned (addr_width-1 downto 0); + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + shared variable RAM : RAMtype; + +begin + + dout_a <= RAM(to_integer(addr_a_r)); + dout_b <= RAM(to_integer(addr_b_r)); + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + addr_a_r <= addr_a; + end if; +end if; +end process; + + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + if we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + addr_b_r <= addr_b; + end if; +end if; +end process; + +end Behavioral; + diff --git a/lib/rams/dpram_2w2r2c_ro_sim.vhd b/lib/rams/dpram_2w2r2c_ro_sim.vhd new file mode 100644 index 0000000..79203ba --- /dev/null +++ b/lib/rams/dpram_2w2r2c_ro_sim.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity dpram_2w2r2c_ro is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + we_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + din_b : in unsigned (data_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_2w2r2c_ro; + +architecture Behavioral of dpram_2w2r2c_ro is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + shared variable RAM : RAMtype; + +begin + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + dout_a <= RAM(to_integer(addr_a)); + end if; +end if; +end process; + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + if we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + dout_b <= RAM(to_integer(addr_b)); + end if; +end if; +end process; + + +end Behavioral; + diff --git a/lib/rams/dpram_2w2r2c_ro_xil.vhd b/lib/rams/dpram_2w2r2c_ro_xil.vhd new file mode 100644 index 0000000..664a144 --- /dev/null +++ b/lib/rams/dpram_2w2r2c_ro_xil.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity dpram_2w2r2c_ro is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + we_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + din_b : in unsigned (data_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_2w2r2c_ro; + +architecture Behavioral of dpram_2w2r2c_ro is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + shared variable RAM : RAMtype; + +begin + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + dout_a <= RAM(to_integer(addr_a)); + end if; +end if; +end process; + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + if we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + dout_b <= RAM(to_integer(addr_b)); + end if; +end if; +end process; + + +end Behavioral; +