diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index fe8d081..b75299d 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -182,6 +182,8 @@ architecture behavior of bui is
 	alias write_fifo_data_out is write_fifo_dout(63 downto 32);
 	alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
 
+	signal read_cycle	: std_logic;
+
 begin
 
 
@@ -202,13 +204,14 @@ cyc_registered_out:
 						cyc		:= '1';
 					end if;
 				elsif SRDY_I = '1' then
-					cyc		:= dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
+					cyc		:= read_cycle;
 				end if;
 			end if;
 		end if;
 	end process;	
 
---	CYC_O			<= not bout_fifo_empty or dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
+	read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) or (dcache_mem_gnt and CYC_O_dcache) or (icache_mem_gnt and CYC_O_icache);
+	
 	STB_O			<= not bout_fifo_empty;
 	ADDR_O			<= bout_fifo_addr_out;
 	DAT_O			<= bout_fifo_data_out;
@@ -297,13 +300,9 @@ inst_bout_fifo: entity work.fifo_sync_dist
 		data_r		=>  bout_fifo_dout
 	);
 	bout_rdy			<= not bout_fifo_full;
-	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
+	bout_fifo_re		<= SRDY_I;
 	
-	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
-						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
-						   STB_O_dcache when dcache_mem_gnt = '1' else
-						   STB_O_icache when icache_mem_gnt = '1' else '0';
-						   
+	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
 
 	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');