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Force VCD

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jens
2022-06-30 22:16:13 +02:00
parent 2c6a0b9c99
commit 6085b37907
3 changed files with 6 additions and 0 deletions
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lib/JBUS/memory/ghdl/.gitignore.templ
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@@ -0,0 +1,4 @@
.gitignore
build/
.gitignore
build/
lib/JBUS/memory/ghdl/tb_ram_wb.make
+1
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@@ -11,5 +11,6 @@ SRCS += $(MOD_PATH)/src/tb_ram_wb.vhd
TARGET := tb_ram_wb TARGET := tb_ram_wb
ENTITY := tb_ram_wb ENTITY := tb_ram_wb
RUN_TIME := 1500ns RUN_TIME := 1500ns
WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/JBUS/memory/ghdl/tb_rom_wb.make
+1
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@@ -10,6 +10,7 @@ SRCS += $(MOD_PATH)/src/tb_rom_wb.vhd
TARGET := tb_rom_wb TARGET := tb_rom_wb
ENTITY := tb_rom_wb ENTITY := tb_rom_wb
RUN_TIME := 1500ns RUN_TIME := 1500ns
WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk