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- removed BURSTLEN from generics

Browse Source 
- fixed burst counter
- fixed SDR PHY

git-svn-id: http://moon:8086/svn/vhdl/trunk@1224 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-25 08:03:05 +00:00
parent 5427d4cae0
commit 5fe93ed9ac
17 changed files with 58 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.fdo
+1
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@@ -11,6 +11,7 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../src/sdram_const.vhd"
vcom -explicit -93 "../src/sdram_config_mt48lc16m16.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo
+23 -4
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@@ -39,8 +39,8 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_fb
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_out
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0_out
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_in
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_out
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_ctrl
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_out
add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_ctrl
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_clk
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_dqm
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_rd
@@ -54,15 +54,34 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ras_n
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_cke
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/drive
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/data_reg_r
add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ctrl_reg
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ctrl_reg
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/we_reg
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/locked
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/error
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/u_tag_pipe
add wave -noupdate -divider {SDRAM Cmd FSM}
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/f_sdrclk
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/rst
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/clk
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/enable
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/tag
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/col_addr
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/mode_word
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cmd
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cmd_we
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cmd_ack
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/phy_ctrl
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/st_sdr
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/st_sdr_next
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cc_preset
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cc_load_en
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cycle_finished
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_load_en
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_finished
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {97053140 ps} 0}
WaveRestoreCursors {{Cursor 1} {73212560 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd
-2
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@@ -32,7 +32,6 @@ use work.sdram_types.all;
entity ctrl_ddr_wb32 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4;
@@ -87,7 +86,6 @@ begin
sdram_ctrl_frontend_wb32 : entity work.sdram_ctrl_frontend_wb32
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd
-2
View File
@@ -32,7 +32,6 @@ use work.sdram_types.all;
entity ctrl_ddr_wb64 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4;
@@ -87,7 +86,6 @@ begin
sdram_ctrl_frontend_wb64 : entity work.sdram_ctrl_frontend_wb64
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
-2
View File
@@ -32,7 +32,6 @@ use work.sdram_types.all;
entity ctrl_sdr_wb32 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4;
@@ -85,7 +84,6 @@ begin
sdram_ctrl_frontend_wb16 : entity work.sdram_ctrl_frontend_wb16
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
+4 -3
View File
@@ -25,6 +25,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.sdram_const.all;
use work.sdram_config.all;
use work.sdram_types.all;
@@ -162,7 +163,7 @@ part_clk <= clk0 after TPD_BOARD_SIM;
begin
if falling_edge(clk0) then
part_data <= (others => 'Z') after TPD_BOARD_SIM;
if (drive = '1') then
if (phy_ctrl.drive_en = '1') then
part_data <= phy_in.wr_data after TPD_BOARD_SIM;
end if;
end if;
@@ -233,8 +234,8 @@ misc_flags_and_data_out:
if phy_ctrl.we = '1' then
phy_out.tag_wr <= u_tag_pipe(0);
end if;
phy_out.wr_data_re <= phy_ctrl.we;
phy_out.rd_data_we <= p(3);
phy_out.wr_data_re <= phy_ctrl.drive_en;
phy_out.rd_data_we <= p(2);
if phy_ctrl.re = '1' then
p := p(p'left-1 downto 0) & '1';
else
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+12 -15
View File
@@ -32,8 +32,7 @@ use work.sdram_types.all;
entity sdram_cmd is
Generic
(
F_SDRCLK : real := 100.0;
BURST_LEN : natural := 2
F_SDRCLK : real := 100.0
);
Port
(
@@ -58,7 +57,6 @@ architecture behaviour of sdram_cmd is
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
signal burst_preset : natural range 0 to 3;
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
@@ -94,7 +92,6 @@ fsm_sdr_state:
cc_preset <= TIMING(cmd);
burst_load_en <= '0';
cmd_ack <= '0';
burst_preset <= BURST_LEN/2-1;
phy_ctrl.re <= '0';
phy_ctrl.drive_en <= '0';
phy_ctrl.we <= '0';
@@ -267,20 +264,20 @@ cycle_counter:
------------------------------------------------------------------------------------------
burst_counter:
process (rst, clk)
variable burst_cnt : natural range 0 to 3;
process (clk)
variable burst_cnt : natural range 0 to 2**(LMR_BL_CURR);
begin
if rst = '1' then
burst_cnt := 0;
elsif rising_edge(clk) then
burst_finished <= '0';
if rising_edge(clk) then
if burst_load_en = '1' then
burst_cnt := burst_preset;
elsif burst_cnt /= 0 then
burst_cnt := burst_cnt - 1;
end if;
if burst_cnt = 0 then
burst_finished <= '0';
burst_cnt := 2**(LMR_BL_CURR);
if 2**(LMR_BL_CURR) = DATA_RATE_FACTOR then
burst_finished <= '1';
end if;
elsif burst_cnt < DATA_RATE_FACTOR then
burst_finished <= '1';
else
burst_cnt := burst_cnt - DATA_RATE_FACTOR;
end if;
end if;
end process;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt46v16m16.vhd
+9 -8
View File
@@ -29,23 +29,24 @@ use work.sdram_const.all;
package sdram_config is
constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
constant PART_ROW_ADDR_WIDTH : positive := 13; --
constant PART_COL_ADDR_WIDTH : positive := 9; --
constant DATA_RATE_FACTOR : positive := 2; -- DDR => twice part data width
constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
constant PART_ROW_ADDR_WIDTH : positive := 13; --
constant PART_COL_ADDR_WIDTH : positive := 9; --
constant PART_DQS_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of data strobe lines
constant PART_DM_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of Data Mask Lines
constant BUS_DATA_WIDTH : positive := 2*PART_DATA_WIDTH; -- DDR => twice part data width
constant BUS_DM_WIDTH : positive := 2*PART_DM_WIDTH; -- DDR => twice part data width
constant BUS_DATA_WIDTH : positive := DATA_RATE_FACTOR*PART_DATA_WIDTH; -- DDR => twice part data width
constant BUS_DM_WIDTH : positive := DATA_RATE_FACTOR*PART_DM_WIDTH; -- DDR => twice part data width
-- DDR SDRAM Hardware defined constants
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
constant ENABLE_PRE_ALL : std_logic := '1';
constant ENABLE_AUTO_PRE : std_logic := '0';
constant LM_BL_CURR : natural := LMR_BL2;
constant LMR_BL_CURR : natural := LMR_BL2;
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+2 -1
View File
@@ -29,6 +29,7 @@ use work.sdram_const.all;
package sdram_config is
constant DATA_RATE_FACTOR : positive := 1; -- DDR => twice part data width
constant PART_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
@@ -46,7 +47,7 @@ package sdram_config is
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
constant ENABLE_PRE_ALL : std_logic := '1';
constant ENABLE_AUTO_PRE : std_logic := '0';
constant LM_BL_CURR : natural := LMR_BL1;
constant LMR_BL_CURR : natural := LMR_BL1;
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+2 -3
View File
@@ -33,7 +33,6 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0
);
Port (
@@ -128,7 +127,7 @@ architecture behaviour of sdram_ctrl is
),
(
cmd => SD_LMR,
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LM_BL_CURR, 3),
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BL_CURR, 3),
wait_cycle => 200
),
(
@@ -168,7 +167,7 @@ architecture behaviour of sdram_ctrl is
),
(
cmd => SD_LMR,
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LM_BL_CURR, 3),
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BL_CURR, 3),
wait_cycle => 200
),
(
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
+3 -4
View File
@@ -26,13 +26,13 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.fifo_ctrl_pkg.all;
use work.sdram_const.all;
use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_ctrl_frontend_wb16 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4
@@ -180,7 +180,6 @@ begin
inst_sdram_ctrl_top : entity work.sdram_ctrl_top
Generic map
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
@@ -216,8 +215,8 @@ begin
write_fifo_dm_in <= not SEL_I(1 downto 0);
cat_fifo_we <= STB_I and rdy;
cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
addr_fifo_in <= ADDR_I(24 downto 2) & "0";
tag_fifo_in <= "000" & ADDR_I(25);
addr_fifo_in <= "000" & ADDR_I(22 downto 2);
tag_fifo_in <= "000" & ADDR_I(2);
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd <= cmd_fifo_out;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
-2
View File
@@ -33,7 +33,6 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend_wb32 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4
@@ -181,7 +180,6 @@ begin
inst_sdram_ctrl_top : entity work.sdram_ctrl_top
Generic map
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
-2
View File
@@ -33,7 +33,6 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend_wb64 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4
@@ -181,7 +180,6 @@ begin
inst_sdram_ctrl_top : entity work.sdram_ctrl_top
Generic map
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+2 -5
View File
@@ -32,7 +32,6 @@ use work.sdram_types.all;
entity sdram_ctrl_top is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : natural := 3
@@ -97,8 +96,7 @@ begin
inst_sdram_ctrl : entity work.sdram_ctrl
Generic map
(
F_SYSCLK => F_SYSCLK,
BURST_LEN => BURST_LEN
F_SYSCLK => F_SYSCLK
)
Port map
(
@@ -144,8 +142,7 @@ begin
inst_sdram_cmd : entity work.sdram_cmd
Generic map
(
F_SDRCLK => F_SDRCLK,
BURST_LEN => BURST_LEN
F_SDRCLK => F_SDRCLK
)
Port map
(
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
-2
View File
@@ -36,7 +36,6 @@ architecture struct of tb_ctrl_ddr_wb32 is
constant CLK_PERIOD : time := 10 ns;
constant TPD_BOARD_SIM : time := 1 ns;
constant SDCLK_PERIOD : time := 7.5 ns;
constant BURST_LEN : natural := 2;
signal sdclk : std_logic := '1';
signal sdclk_fb : std_logic;
@@ -113,7 +112,6 @@ begin
uut : entity work.ctrl_ddr_wb32
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => 100.000,
F_SDRCLK => 133.333,
FIFO_DEPTH => 4,
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
-2
View File
@@ -36,7 +36,6 @@ architecture struct of tb_ctrl_ddr_wb64 is
constant CLK_PERIOD : time := 10 ns;
constant TPD_BOARD_SIM : time := 1 ns;
constant SDCLK_PERIOD : time := 10 ns;
constant BURST_LEN : natural := 2;
signal sdclk : std_logic := '1';
signal sdclk_fb : std_logic;
@@ -119,7 +118,6 @@ begin
uut : entity work.ctrl_ddr_wb64
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => 100.000,
F_SDRCLK => 100.000,
FIFO_DEPTH => 4,
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd
-2
View File
@@ -36,7 +36,6 @@ architecture struct of tb_ctrl_sdr_wb32 is
constant CLK_PERIOD : time := 10 ns;
constant TPD_BOARD_SIM : time := 3 ns;
constant SDCLK_PERIOD : time := 10 ns;
constant BURST_LEN : natural := 2;
signal sdclk : std_logic := '1';
signal sdclk_fb : std_logic;
@@ -111,7 +110,6 @@ begin
uut : entity work.ctrl_sdr_wb32
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => 100.000,
F_SDRCLK => 100.000,
FIFO_DEPTH => 4,