diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
index afc6653..2e57844 100644
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ b/lib/filter/src/fir_semi_parallel.vhd
@@ -83,7 +83,6 @@ architecture Behavioral of fir_semi_parallel is
 	signal ce0					: std_logic;
 	signal ce_array				: unsigned(nstages downto 0);
 	signal coef_addr			: unsigned(coef_addr_nbits-1 downto 0);
-	signal stage_addr			: unsigned(NextExpBaseTwo(nstages)-1 downto 0);
 	
 	SIGNAL x			: stage_array_t;
 	SIGNAL xo			: stage_array_t;
@@ -107,16 +106,11 @@ begin
 	assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure;
 	assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure;
 
-	coef_addr	<= to_unsigned(h_addr, coef_addr_nbits);
-	stage_addr	<= coef_addr(coef_addr'left downto NextExpBaseTwo(ntaps_per_stage));
-	
 	x(0)		<= resize(din_r, x(0));
 	y(0)		<= to_sfixed(0.0, y(0));
 
 	accu_load	<= accu_ld_pipe(accu_ld_pipe'left);
 	
-	coef_din	<= unsigned(h_in);
-	
 din_register:	
 	process(clk)
 	begin
@@ -140,13 +134,20 @@ accu_load_pipe:
 	end process;
 
 coef_we_gen:
-	process(stage_addr)
+	process(clk)
 	variable i : natural range 0 to nstages-1;
-	
+	variable caddr	: unsigned(coef_addr_nbits-1 downto 0);
+	variable saddr	: unsigned(NextExpBaseTwo(nstages)-1 downto 0);
 	begin
-		i := to_integer(stage_addr);
-		coef_we		<= (others => '0');
-		coef_we(i)	<= '1';
+		if rising_edge(clk) then
+			caddr		:= to_unsigned(h_addr, coef_addr_nbits);
+			saddr		:= caddr(caddr'left downto NextExpBaseTwo(ntaps_per_stage));
+			i 			:= to_integer(saddr);
+			coef_we		<= (others => '0');
+			coef_we(i)	<= '1';
+			coef_din	<= unsigned(h_in);
+			coef_addr	<= caddr;
+		end if;	
 	end process;
 
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