- renamed fifo_*sync_ctrl

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@298 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/sim/tb_mips_top.fdo

@@ -9,7 +9,7 @@ vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
 
 # FIFOS
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_sync_dist.vhd"
 
 # UART

lib/CPUs/MIPS/todo.txt

@@ -1,5 +1,17 @@
 2008-10-26
-- Optimierung: MUL32x32 primitive für Virtex-4
+- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
+- Area-Optimierung: MUL32x32 primitive für Virtex-4
+- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
 - External COP 1..3 interface
 - FPU (COP1)
 - MMU
+
+2008-10-27
+- Area vs. speed : Pipeline-stall statt forwarding
+- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
+          - 1,2,4-way assoziative
+          - 2nd-Level cache in System
+          - Write-back policy
+
+2008-11-15
+- Bus exceptions IBE DBE (BUI/Cache restart notwendig)

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo

@@ -25,13 +25,13 @@ add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re
 add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/was_write
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/was_write
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw_next
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw_next
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_full
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_empty
 add wave -noupdate -divider {Write FIFO}
 add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r
 add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w
@@ -39,17 +39,17 @@ add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw_next
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw_next
 add wave -noupdate -divider {Command FIFO}
 add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r
 add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we
 add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_full
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_full
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 4} {13893123 ps} 0}
 configure wave -namecolwidth 172

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo

@@ -3,8 +3,8 @@
 
 vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo

@@ -27,8 +27,11 @@ add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_fronten
 add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full
 add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full
 add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_in
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_out
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_data_vld
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {27951315 ps} 0}
+WaveRestoreCursors {{Cursor 4} {27802417 ps} 0}
 configure wave -namecolwidth 172
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -42,4 +45,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {0 ps} {42 us}
+WaveRestoreZoom {27712165 ps} {27944343 ps}

lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd

@@ -68,7 +68,7 @@ begin
 	fifo_afull <= almost_full;
 	fifo_aempty <= almost_empty;
 
-	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+	inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
 	GENERIC MAP
 	(
 		addr_width			=> addr_width,

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo

@@ -5,7 +5,7 @@ vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo

@@ -5,7 +5,7 @@ vlib work
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"

lib/VGA_ctrl/sim/tb_vga_frontend.fdo

@@ -5,7 +5,7 @@ vlib work
 vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
 vcom -explicit  -93 "../src/fonts/char_rom_c64.vhd"
 vcom -explicit  -93 "../src/vga_types.vhd"

lib/VGA_ctrl/sim/tb_vga_frontend64.fdo

@@ -5,7 +5,7 @@ vlib work
 vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
 vcom -explicit  -93 "../src/fonts/char_rom_c64.vhd"
 vcom -explicit  -93 "../src/vga_types.vhd"

lib/ac97_ctrl/sim/tb_ac97_wb.fdo

@@ -3,7 +3,7 @@
 ##
 vlib work
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../misc/dpram_1w1r_dist.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_sync_dist.vhd"
 vcom -explicit  -93 "../../misc/singleshot.vhd"

lib/ac97_ctrl/src/core/ac97_wb.vhd

@@ -5,7 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
 ENTITY ac97_wb IS
 	Generic
 	(
-		fifo_depth		: natural := 4
+		fifo_depth		: natural := 8
 	);
 	Port
 	(
@@ -76,15 +76,8 @@ ARCHITECTURE behavior OF ac97_wb IS
 	signal tx_fifo_almost_full		: std_logic;
 	signal tx_fifo_almost_empty		: std_logic;
 
-	signal rx_data_start			: std_logic;
+	signal rx_data_irq				: std_logic;
-	signal rx_fifo_din				: unsigned(pcm_data_width-1 downto 0);
+	signal rx_data_ack				: std_logic;
-	signal rx_fifo_dout				: unsigned(pcm_data_width-1 downto 0);
-	signal rx_fifo_re				: std_logic;
-	signal rx_fifo_we				: std_logic;
-	signal rx_fifo_full				: std_logic;
-	signal rx_fifo_empty			: std_logic;
-	signal rx_fifo_almost_full		: std_logic;
-	signal rx_fifo_almost_empty		: std_logic;
 
 	signal ac97_stat				: unsigned(31 downto 0);
 	signal addr_reg					: unsigned(31 downto 0);
@@ -92,6 +85,10 @@ ARCHITECTURE behavior OF ac97_wb IS
 	signal int_en_frame_sync		: std_logic;
 	signal int_en_rx				: std_logic;
 	signal int_en_tx				: std_logic;
+	signal rx_en					: std_logic;
+	signal tx_en					: std_logic;
+	signal rx_fifo_rst				: std_logic;
+	signal tx_fifo_rst				: std_logic;
 
 	function GetRequest(slot1 : unsigned) return unsigned is
 	variable res : unsigned(3 to 12);
@@ -104,10 +101,13 @@ ARCHITECTURE behavior OF ac97_wb IS
 
 	end GetRequest;
 
+	type ac_state_t is (reset, idle, pcm_3, pcm_4);
+	signal rx_state, rx_state_n : ac_state_t;
+
 begin
 
 	SRDY_O			<= CYC_I;
-	INT_O			<= (rx_fifo_almost_full and int_en_rx) or (tx_fifo_almost_empty and int_en_tx) or (sync_frame and int_en_frame_sync) ;
+	INT_O			<= (rx_data_irq and int_en_rx) or (not tx_fifo_full and int_en_tx) or (sync_frame and int_en_frame_sync) ;
 	
 	rx_frame_valid	<= ac_slot_valid(0);
 	sync_frame		<= ac_sync_strobe(0);
@@ -117,7 +117,7 @@ begin
 	
 	ac_stat_read	<= not addr_reg(9);
 	ac_stat_valid	<= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0';
-	ac97_stat		<= ac_ready & "000" & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & not rx_fifo_almost_empty & tx_fifo_almost_full & stat_valid & cmd_pending;
+	ac97_stat		<= ac_ready & '0' & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & '0' & tx_fifo_full & rx_data_irq & tx_fifo_almost_full & stat_valid & cmd_pending;
 	
 command_logic:
 	process (CLK_I)
@@ -156,8 +156,8 @@ command_register:
 	begin
 		if rising_edge(CLK_I) then
 			if cmd_reg_we = '1' and cmd_pending = '0' then
-				ac_cmd_addr			<= ac_stat_read & addr_reg(8 downto 2) & X"000";
+				ac_cmd_addr		<= ac_stat_read & addr_reg(8 downto 2) & X"000";
-				ac_cmd_data			<= data_reg(stat_data_width-1 downto 0) & X"0";
+				ac_cmd_data		<= data_reg(stat_data_width-1 downto 0) & X"0";
 			end if;	
 		end if;	
 	end process;
@@ -179,33 +179,34 @@ status_register:
 	end process;
 
 	-- Instantiate synchronous FIFO
-inst_tx_fifo: entity work.fifo_sync_dist
+inst_tx_fifo: entity work.fifo_sync
 	GENERIC MAP
 	(
 		addr_width			=> fifo_depth,
 		data_width			=> pcm_data_width,
-		almost_full_thresh	=> 12,
+		almost_full_thresh	=> 90*(2**fifo_depth)/100,
-		almost_empty_thresh	=> 4
+		almost_empty_thresh	=> 10*(2**fifo_depth)/100
 	)
 	PORT MAP
 	(
-		rst			=>	RST_I,
+		rst			=>	tx_fifo_rst,
 		clk			=>	CLK_I,
 		we			=>	tx_fifo_we,
 		re			=>	tx_fifo_re,
 		fifo_full	=>	tx_fifo_full,
 		fifo_empty	=>	tx_fifo_empty,
-		fifo_afull	=>	open,
+		fifo_afull	=>	tx_fifo_almost_full,
-		fifo_aempty	=>	open,
+		fifo_aempty	=>	tx_fifo_almost_empty,
 		data_w		=>  tx_fifo_din,
 		data_r		=>  tx_fifo_dout
 	);
-
+	tx_fifo_rst		<= not tx_en or RST_I;
+	
 tx_logic:
 	process (CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if RST_I = '1' then
+			if RST_I = '1' or tx_en = '0' then
 				ac_tx_pcm_addr 	<= "0011";
 				tx_data_start	<= '0';
 			elsif sync_tx = '1' and (request(3) and request(4)) = '1' then
@@ -224,50 +225,23 @@ tx_logic:
 	
 	tx_fifo_din		<= data_reg(pcm_data_width-1 downto 0);
 	
-	-- Instantiate synchronous FIFO
+	ac_rx_pcm_addr	<= addr_reg(5 downto 2);
-inst_rx_fifo: entity work.fifo_sync_dist
-	GENERIC MAP
-	(
-		addr_width			=> fifo_depth,
-		data_width			=> pcm_data_width,
-		almost_full_thresh	=> 12,
-		almost_empty_thresh	=> 4
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	CLK_I,
-		we			=>	rx_fifo_we,
-		re			=>	rx_fifo_re,
-		fifo_full	=>	rx_fifo_full,
-		fifo_empty	=>	rx_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  rx_fifo_din,
-		data_r		=>  rx_fifo_dout
-	);
-
-	rx_fifo_din			<= ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
 
 rx_logic:
 	process (CLK_I)
 	begin
 		if rising_edge(CLK_I) then
 			if RST_I = '1' then
-				ac_rx_pcm_addr 	<= "0011";
+				rx_data_irq	<= '0';
-				rx_data_start 	<= '0';
+			elsif rx_frame_valid = '1' and sync_frame = '1' then 
-			elsif (rx_frame_valid and sync_frame) = '1' and (ac_slot_valid(3) and ac_slot_valid(4)) = '1' then
+				if ac_slot_valid(3) = '1' and ac_slot_valid(4) = '1' then
-				ac_rx_pcm_addr 	<= "0011";
+					rx_data_irq	<= rx_en;
-				rx_data_start 	<= '1';
+				end if;
-			elsif ac_rx_pcm_addr /= "0100" then
+			elsif rx_data_ack = '1' then
-				ac_rx_pcm_addr	<= ac_rx_pcm_addr + 1;
+				rx_data_irq	<= '0';
-			else
+			end if;
-				rx_data_start	<= '0';
+		end if;
-			end if;	
+	end process;	
-		end if;	
-	end process;
-
-	rx_fifo_we	<= rx_data_start;
 
 inst_ac_io : entity work.ac_io
     PORT MAP
@@ -301,17 +275,20 @@ slave_data_out:
 	begin
 		
 		if rising_edge(CLK_I) then
+			tx_fifo_we		<= '0';
+			stat_reg_re		<= '0';
+			cmd_reg_we		<= '0';
+			rx_data_ack		<= '0';
+			ACK_O			<= '0';
 			if RST_I = '1' then
+				addr_reg			<= (others => '0');
 				int_en_frame_sync	<= '0';
 				int_en_rx			<= '0';
 				int_en_tx			<= '0';
+				tx_en				<= '0';
+				rx_en				<= '0';
 			else
-				DAT_O			<= (others => '-');
+--				DAT_O			<= (others => '-');
-				rx_fifo_re		<= '0';
-				tx_fifo_we		<= '0';
-				stat_reg_re		<= '0';
-				cmd_reg_we		<= '0';
-				ACK_O			<= '0';
 
 				if (STB_I and CYC_I) = '1' then
 					ACK_O		<= not WE_I;
@@ -324,6 +301,8 @@ slave_data_out:
 							int_en_frame_sync	<= DAT_I(0);
 							int_en_tx			<= DAT_I(1);
 							int_en_rx			<= DAT_I(2);
+							tx_en				<= DAT_I(4);
+							rx_en				<= DAT_I(5);
 						end if;
 					when "01" =>
 						addr_reg			<= ADDR_I;
@@ -333,11 +312,11 @@ slave_data_out:
 						DAT_O				<= (31 downto stat_data_width => '0') & stat_reg;
 
 					when "10" =>
+						rx_data_ack			<= not WE_I;
 						addr_reg			<= ADDR_I;
 						data_reg			<= DAT_I;
-						rx_fifo_re			<= not WE_I;
 						tx_fifo_we			<= WE_I;
-						DAT_O				<= (31 downto pcm_data_width => '0') & rx_fifo_dout;
+						DAT_O				<= (31 downto pcm_data_width => ac_rx_pcm_data(ac_data_width-1)) & ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
 
 					when others => null;
 

lib/filter/src/tb_fir_semi_parallel.vhd

@@ -31,8 +31,8 @@ use work.PCK_FIO.all;
 ENTITY tb_fir_semi_parallel IS
 	Generic
 	(
-		ntaps_per_stage		: integer := 16;
+		ntaps_per_stage		: integer := 32;
-		nstages				: integer := 4;
+		nstages				: integer := 2;
 		nbits_in			: integer := 32;
 		nbits_in_frac		: integer := 30;
 		nbits_stages		: integer := 32;
@@ -141,7 +141,7 @@ BEGIN
 	(
 		ntaps_per_stage		=> ntaps_per_stage,
 		nstages				=> nstages,
-		pipe_latency		=> 4,
+		pipe_latency		=> 5,
 		nbits_in			=> nbits_in,
 		nbits_in_frac		=> nbits_in_frac,
 		nbits_stages		=> nbits_stages,

lib/radio/ddc/sim/tb_ddc.fdo

@@ -21,7 +21,7 @@ vcom -explicit  -93 "../../decimator/CIC/src/cic_i_pipe.vhd"
 vcom -explicit  -93 "../../decimator/CIC/src/cic_c_pipe.vhd"
 vcom -explicit  -93 "../../decimator/CIC/src/cic_decim_pipe.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/ddc.vhd"
 vcom -explicit  -93 "../src/tb_ddc.vhd"

lib/radio/ddc/src/syn_ddc.vhd

@@ -134,8 +134,8 @@ BEGIN
 		dout_q				=> ddc_dout_q
 	);
 	
-	ddc_din_i	<= to_sfixed(din_i, ddc_din_i);
+	ddc_din_i	<= sfixed(din_i);
-	ddc_din_q	<= to_sfixed(din_q, ddc_din_q);
+	ddc_din_q	<= sfixed(din_q);
 	
 	dout_i	<= signed(ddc_dout_i);
 	dout_q	<= signed(ddc_dout_q);