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- renamed fifo_*sync_ctrl

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git-svn-id: http://moon:8086/svn/vhdl/trunk@298 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-30 21:30:21 +00:00
parent b3da8c3d7b
commit 5ed37017b5
21 changed files with 105 additions and 111 deletions
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lib/ac97_ctrl/sim/tb_ac97_wb.fdo
+1 -1
View File
@@ -3,7 +3,7 @@
##
vlib work
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r_dist.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_sync_dist.vhd"
vcom -explicit -93 "../../misc/singleshot.vhd"
lib/ac97_ctrl/src/core/ac97_wb.vhd
+47 -68
View File
@@ -5,7 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
ENTITY ac97_wb IS
Generic
(
fifo_depth : natural := 4
fifo_depth : natural := 8
);
Port
(
@@ -76,15 +76,8 @@ ARCHITECTURE behavior OF ac97_wb IS
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal rx_data_start : std_logic;
signal rx_fifo_din : unsigned(pcm_data_width-1 downto 0);
signal rx_fifo_dout : unsigned(pcm_data_width-1 downto 0);
signal rx_fifo_re : std_logic;
signal rx_fifo_we : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_data_irq : std_logic;
signal rx_data_ack : std_logic;
signal ac97_stat : unsigned(31 downto 0);
signal addr_reg : unsigned(31 downto 0);
@@ -92,6 +85,10 @@ ARCHITECTURE behavior OF ac97_wb IS
signal int_en_frame_sync : std_logic;
signal int_en_rx : std_logic;
signal int_en_tx : std_logic;
signal rx_en : std_logic;
signal tx_en : std_logic;
signal rx_fifo_rst : std_logic;
signal tx_fifo_rst : std_logic;
function GetRequest(slot1 : unsigned) return unsigned is
variable res : unsigned(3 to 12);
@@ -104,10 +101,13 @@ ARCHITECTURE behavior OF ac97_wb IS
end GetRequest;
type ac_state_t is (reset, idle, pcm_3, pcm_4);
signal rx_state, rx_state_n : ac_state_t;
begin
SRDY_O <= CYC_I;
INT_O <= (rx_fifo_almost_full and int_en_rx) or (tx_fifo_almost_empty and int_en_tx) or (sync_frame and int_en_frame_sync) ;
INT_O <= (rx_data_irq and int_en_rx) or (not tx_fifo_full and int_en_tx) or (sync_frame and int_en_frame_sync) ;
rx_frame_valid <= ac_slot_valid(0);
sync_frame <= ac_sync_strobe(0);
@@ -117,7 +117,7 @@ begin
ac_stat_read <= not addr_reg(9);
ac_stat_valid <= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0';
ac97_stat <= ac_ready & "000" & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & not rx_fifo_almost_empty & tx_fifo_almost_full & stat_valid & cmd_pending;
ac97_stat <= ac_ready & '0' & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & '0' & tx_fifo_full & rx_data_irq & tx_fifo_almost_full & stat_valid & cmd_pending;
command_logic:
process (CLK_I)
@@ -156,8 +156,8 @@ command_register:
begin
if rising_edge(CLK_I) then
if cmd_reg_we = '1' and cmd_pending = '0' then
ac_cmd_addr <= ac_stat_read & addr_reg(8 downto 2) & X"000";
ac_cmd_data <= data_reg(stat_data_width-1 downto 0) & X"0";
ac_cmd_addr <= ac_stat_read & addr_reg(8 downto 2) & X"000";
ac_cmd_data <= data_reg(stat_data_width-1 downto 0) & X"0";
end if;
end if;
end process;
@@ -179,33 +179,34 @@ status_register:
end process;
-- Instantiate synchronous FIFO
inst_tx_fifo: entity work.fifo_sync_dist
inst_tx_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => pcm_data_width,
almost_full_thresh => 12,
almost_empty_thresh => 4
almost_full_thresh => 90*(2**fifo_depth)/100,
almost_empty_thresh => 10*(2**fifo_depth)/100
)
PORT MAP
(
rst => RST_I,
rst => tx_fifo_rst,
clk => CLK_I,
we => tx_fifo_we,
re => tx_fifo_re,
fifo_full => tx_fifo_full,
fifo_empty => tx_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
fifo_afull => tx_fifo_almost_full,
fifo_aempty => tx_fifo_almost_empty,
data_w => tx_fifo_din,
data_r => tx_fifo_dout
);
tx_fifo_rst <= not tx_en or RST_I;
tx_logic:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
if RST_I = '1' or tx_en = '0' then
ac_tx_pcm_addr <= "0011";
tx_data_start <= '0';
elsif sync_tx = '1' and (request(3) and request(4)) = '1' then
@@ -224,50 +225,23 @@ tx_logic:
tx_fifo_din <= data_reg(pcm_data_width-1 downto 0);
-- Instantiate synchronous FIFO
inst_rx_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => fifo_depth,
data_width => pcm_data_width,
almost_full_thresh => 12,
almost_empty_thresh => 4
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => rx_fifo_we,
re => rx_fifo_re,
fifo_full => rx_fifo_full,
fifo_empty => rx_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => rx_fifo_din,
data_r => rx_fifo_dout
);
rx_fifo_din <= ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
ac_rx_pcm_addr <= addr_reg(5 downto 2);
rx_logic:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ac_rx_pcm_addr <= "0011";
rx_data_start <= '0';
elsif (rx_frame_valid and sync_frame) = '1' and (ac_slot_valid(3) and ac_slot_valid(4)) = '1' then
ac_rx_pcm_addr <= "0011";
rx_data_start <= '1';
elsif ac_rx_pcm_addr /= "0100" then
ac_rx_pcm_addr <= ac_rx_pcm_addr + 1;
else
rx_data_start <= '0';
end if;
end if;
end process;
rx_fifo_we <= rx_data_start;
rx_data_irq <= '0';
elsif rx_frame_valid = '1' and sync_frame = '1' then
if ac_slot_valid(3) = '1' and ac_slot_valid(4) = '1' then
rx_data_irq <= rx_en;
end if;
elsif rx_data_ack = '1' then
rx_data_irq <= '0';
end if;
end if;
end process;
inst_ac_io : entity work.ac_io
PORT MAP
@@ -301,17 +275,20 @@ slave_data_out:
begin
if rising_edge(CLK_I) then
tx_fifo_we <= '0';
stat_reg_re <= '0';
cmd_reg_we <= '0';
rx_data_ack <= '0';
ACK_O <= '0';
if RST_I = '1' then
addr_reg <= (others => '0');
int_en_frame_sync <= '0';
int_en_rx <= '0';
int_en_tx <= '0';
tx_en <= '0';
rx_en <= '0';
else
DAT_O <= (others => '-');
rx_fifo_re <= '0';
tx_fifo_we <= '0';
stat_reg_re <= '0';
cmd_reg_we <= '0';
ACK_O <= '0';
-- DAT_O <= (others => '-');
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
@@ -324,6 +301,8 @@ slave_data_out:
int_en_frame_sync <= DAT_I(0);
int_en_tx <= DAT_I(1);
int_en_rx <= DAT_I(2);
tx_en <= DAT_I(4);
rx_en <= DAT_I(5);
end if;
when "01" =>
addr_reg <= ADDR_I;
@@ -333,11 +312,11 @@ slave_data_out:
DAT_O <= (31 downto stat_data_width => '0') & stat_reg;
when "10" =>
rx_data_ack <= not WE_I;
addr_reg <= ADDR_I;
data_reg <= DAT_I;
rx_fifo_re <= not WE_I;
tx_fifo_we <= WE_I;
DAT_O <= (31 downto pcm_data_width => '0') & rx_fifo_dout;
DAT_O <= (31 downto pcm_data_width => ac_rx_pcm_data(ac_data_width-1)) & ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
when others => null;