- renamed fifo_*sync_ctrl

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git-svn-id: http://moon:8086/svn/vhdl/trunk@298 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/sim/tb_mips_top.fdo

@@ -9,7 +9,7 @@ vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
 
 # FIFOS
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_sync_dist.vhd"
 
 # UART

lib/CPUs/MIPS/todo.txt

@@ -1,5 +1,17 @@
 2008-10-26
-- Optimierung: MUL32x32 primitive für Virtex-4
+- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
+- Area-Optimierung: MUL32x32 primitive für Virtex-4
+- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
 - External COP 1..3 interface
 - FPU (COP1)
 - MMU
+
+2008-10-27
+- Area vs. speed : Pipeline-stall statt forwarding
+- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
+          - 1,2,4-way assoziative
+          - 2nd-Level cache in System
+          - Write-back policy
+
+2008-11-15
+- Bus exceptions IBE DBE (BUI/Cache restart notwendig)