From 5d7fed125974a4eeff7b40e61862029298eadf48 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 24 Oct 2009 20:27:57 +0000 Subject: [PATCH] - removed force-TX-IRQ and TX-IRQ acknowledge - TX-IRQ is always asserted if tx-FIFO is empty and tx-inten is active. If TX-INT is not desired, it has to be switched off manually by TX-Inten. Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@532 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/uart/uart_wb.vhd | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd index f13bb4f..f5acad0 100644 --- a/lib/uart/uart_wb.vhd +++ b/lib/uart/uart_wb.vhd @@ -74,11 +74,8 @@ ARCHITECTURE behavior OF uart_wb IS signal tx_int_en : std_logic; signal irq_rx : std_logic; signal irq_tx : std_logic; - signal irq_tx_ack : std_logic; signal tx_complete : std_logic; signal tx_empty : std_logic; - signal tx_busy : std_logic; - signal force_irq_tx : std_logic; begin @@ -90,8 +87,6 @@ registers_write: begin if rising_edge(CLK_I) then reg_we_uart_tx <= '0'; - irq_tx_ack <= '0'; - force_irq_tx <= '0'; if RST_I = '1' then reg_uart_baud <= to_unsigned(53, 16); rx_int_en <= '0'; @@ -106,8 +101,6 @@ registers_write: when "0001" => rx_int_en <= DAT_I(6); tx_int_en <= DAT_I(5); - irq_tx_ack <= DAT_I(8); - force_irq_tx <= DAT_I(9); when "0010" => reg_uart_baud <= DAT_I(15 downto 0); @@ -161,25 +154,11 @@ baud_timer: end if; end process; -tx_interrupt: +irq_register: process(CLK_I) begin if rising_edge(CLK_I) then - if RST_I = '1' then - irq_tx <= '0'; - tx_busy <= '0'; - elsif irq_tx_ack = '1' then - irq_tx <= '0'; - else - if force_irq_tx = '1' then - irq_tx <= tx_int_en; - elsif tx_empty = '0' then - tx_busy <= '1'; - elsif tx_busy = '1' then - irq_tx <= tx_int_en; - tx_busy <= '0'; - end if; - end if; + irq_tx <= tx_empty and tx_int_en; irq_rx <= rx_data_present and rx_int_en; end if; end process;