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[Mips_sys]

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- added GMII clock gen

git-svn-id: http://moon:8086/svn/vhdl/trunk@1332 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-12-13 13:12:56 +00:00
parent a6fe149b7a
commit 5d542e783b
2 changed files with 24 additions and 2 deletions
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projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf
+4
View File
@@ -31,6 +31,10 @@ NET "vga_clk" TNM_NET = "vga_clk";
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %; TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG; TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET "gmii_clk" TNM_NET = "gmii_clk";
TIMESPEC "TS_gmii_clk" = PERIOD "gmii_clk" 8.0 ns HIGH 50 %;
TIMESPEC "TS_unrelate_GMII" = FROM sys_clk TO gmii_clk TIG;
NET "sys_clk_in" LOC = "AE14"; NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33; NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6"; NET "sys_rst_n_in" LOC = "D6";
projects/mips_sys/src/mips_sys.vhd
+20 -2
View File
@@ -367,6 +367,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal ps2_1_data_rx : std_logic; signal ps2_1_data_rx : std_logic;
signal ps2_1_clk_tx : std_logic; signal ps2_1_clk_tx : std_logic;
signal ps2_1_data_tx : std_logic; signal ps2_1_data_tx : std_logic;
signal gmii_clk : std_logic;
-- Arbiter -- Arbiter
constant ARB_MAX_MASTER : natural := 2; constant ARB_MAX_MASTER : natural := 2;
@@ -492,6 +493,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal mem_area : mem_area_t; signal mem_area : mem_area_t;
attribute KEEP : string; attribute KEEP : string;
attribute KEEP of gmii_clk : signal is "TRUE";
attribute KEEP of vga_clk : signal is "TRUE"; attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of CLK_O : signal is "TRUE"; attribute KEEP of CLK_O : signal is "TRUE";
attribute KEEP of RST_O : signal is "TRUE"; attribute KEEP of RST_O : signal is "TRUE";
@@ -542,7 +544,8 @@ BEGIN
sys_vga_clk <= vga_clk; sys_vga_clk <= vga_clk;
vga_ce <= not vga_rst; vga_ce <= not vga_rst;
sys_phy_gtx_clk <= gmii_clk;
--------------------------------------------------------------- ---------------------------------------------------------------
-- Arbiter -- Arbiter
MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
@@ -925,6 +928,21 @@ inst_clockgen_vga : entity work.clockgen
clk_out => vga_clk clk_out => vga_clk
); );
inst_clockgen_gmii : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
clk_out_freq => 125.0
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in,
clk_in => sys_clk_in,
rst_out => open,
clk_out => gmii_clk
);
inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64 inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64
GENERIC MAP GENERIC MAP
( (
@@ -1149,7 +1167,7 @@ inst_emac_top_jb : entity work.emac_top_jb
mii_tx_en => sys_phy_tx_en, mii_tx_en => sys_phy_tx_en,
mii_tx_er => sys_phy_tx_er, mii_tx_er => sys_phy_tx_er,
mii_tx => sys_phy_tx, mii_tx => sys_phy_tx,
mii_gtx_clk => sys_phy_gtx_clk, mii_gtx_clk => gmii_clk,
mii_crs => sys_phy_crs, mii_crs => sys_phy_crs,
mii_col => sys_phy_col mii_col => sys_phy_col