diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
index 9639deb..a14c2e0 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -63,6 +63,7 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
 	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
 	signal SDAT_O			: unsigned(31 downto 0) := (others => '-');
+	signal rdy				: std_logic := '0';
 
 	-- VGA signals
 	signal vga_clk			: std_logic := '1';
@@ -130,6 +131,13 @@ inst_vga_frontend64 : entity work.vga_frontend64
 
 	vga_en		<= not RST_O;
 
+rdy_GEN: process
+	begin
+		wait for 3*CLK_PERIOD/2;
+		wait until rising_edge(CLK_O);
+		rdy <= not rdy;
+	end process;
+
 CLK_GEN: process
 	begin
 		wait for CLK_PERIOD/2;
@@ -143,18 +151,34 @@ VGA_CLK_GEN: process
 	end process;
 
 -- Slave
-	SRDY_O	<= CYC_I;
+	SRDY_O	<= CYC_I and rdy;
 	
 	process(CLK_O)
+	variable ack_v : unsigned(11 downto 0);
+	type arr64_t is array (11 downto 0) of unsigned(63 downto 0);
+	variable dat_v : arr64_t;
+	variable res: unsigned(63 downto 0);
+	variable count: unsigned(31 downto 0);
 	begin
 		if rising_edge(CLK_O) then
 			if RST_O = '1' then
-				MDAT_O	<= X"00000000_00000000";
-			elsif (CYC_I and STB_I) = '1' then
-				MDAT_O	<= MDAT_O + 1;
-				ACK_O	<= '1';
+				count	:= X"00000000";
+				for i in 0 to 11 loop
+					dat_v(i)	:= X"FFFFFFFF_FFFFFFFF";
+					ack_v(i)	:= '0';
+				end loop;
 			else
-				ACK_O	<= '0';
+				if (CYC_I and STB_I) = '1' and rdy = '1' then
+					res		:= ADDR_I & count;
+					dat_v	:= dat_v(10 downto 0) & res;
+					ack_v	:= ack_v(10 downto 0) & '1';
+					count 	:= count + 8;
+				else
+					dat_v	:= dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF";
+					ack_v	:= ack_v(10 downto 0) & '0';
+				end if;
+				MDAT_O	<= dat_v(dat_v'left);
+				ACK_O	<= ack_v(ack_v'left);
 			end if;
 		end if;
 	end process;