From 5c6c1fd1cd81bcb88fe89074ee3f12377b57c726 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 14 May 2015 16:14:15 +0000 Subject: [PATCH] - added git-svn-id: http://moon:8086/svn/vhdl/trunk@1082 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/rams/dpram_1w1r2c_ra_alt.vhd | 80 ++++++++++++++++++++++++++++++ lib/rams/dpram_1w1r2c_ro_alt.vhd | 80 ++++++++++++++++++++++++++++++ lib/rams/dpram_2w2r2c_ra_alt.vhd | 85 ++++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+) create mode 100644 lib/rams/dpram_1w1r2c_ra_alt.vhd create mode 100644 lib/rams/dpram_1w1r2c_ro_alt.vhd create mode 100644 lib/rams/dpram_2w2r2c_ra_alt.vhd diff --git a/lib/rams/dpram_1w1r2c_ra_alt.vhd b/lib/rams/dpram_1w1r2c_ra_alt.vhd new file mode 100644 index 0000000..727bc16 --- /dev/null +++ b/lib/rams/dpram_1w1r2c_ra_alt.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity dpram_1w1r2c_ra is + Generic ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_1w1r2c_ra; + +architecture Behavioral of dpram_1w1r2c_ra is + + + -- Build a 2-D array type for the RAM + subtype word_t is unsigned((data_width-1) downto 0); + type memory_t is array(2**addr_width-1 downto 0) of word_t; + + -- Declare the RAM signal. + signal ram : memory_t; + +begin + + process(clk_a) + begin + if(rising_edge(clk_a)) then + if(we_a = '1' and en_a = '1') then + ram(to_integer(addr_a)) <= din_a; + end if; + end if; + end process; + + process(clk_b) + begin + if(rising_edge(clk_b)) then + if(en_b = '1') then + dout_b <= ram(to_integer(addr_b)); + end if; + end if; + end process; + +end Behavioral; + diff --git a/lib/rams/dpram_1w1r2c_ro_alt.vhd b/lib/rams/dpram_1w1r2c_ro_alt.vhd new file mode 100644 index 0000000..4e6fd30 --- /dev/null +++ b/lib/rams/dpram_1w1r2c_ro_alt.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity dpram_1w1r2c_ro is + Generic ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_1w1r2c_ro; + +architecture Behavioral of dpram_1w1r2c_ro is + + constant depth : integer := 2**addr_width; + type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); + signal RAM : RAMtype; + +begin + + +process (clk_a) +begin +if clk_a'event and clk_a = '1' then + if en_a = '1' then + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; + end if; + end if; +end if; +end process; + +process (clk_b) +begin +if clk_b'event and clk_b = '1' then + if en_b = '1' then + dout_b <= RAM(to_integer(addr_b)); + end if; +end if; +end process; + + +end Behavioral; + diff --git a/lib/rams/dpram_2w2r2c_ra_alt.vhd b/lib/rams/dpram_2w2r2c_ra_alt.vhd new file mode 100644 index 0000000..5bf5cac --- /dev/null +++ b/lib/rams/dpram_2w2r2c_ra_alt.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------- +-- Project: Dual-Port RAM with 1 clock latency for simulation +-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity dpram_2w2r2c_ra is + Generic + ( + addr_width : integer := 3; + data_width : integer := 8 + ); + Port + ( + clk_a : in STD_LOGIC; + clk_b : in STD_LOGIC; + en_a : in STD_LOGIC; + en_b : in STD_LOGIC; + we_a : in STD_LOGIC; + we_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + din_b : in unsigned (data_width-1 downto 0); + dout_a : out unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) + ); +end dpram_2w2r2c_ra; + +architecture Behavioral of dpram_2w2r2c_ra is + + constant depth : integer := 2**addr_width; + subtype word_t is unsigned (data_width-1 downto 0); + type RAMtype is array (0 to depth-1) of word_t; + shared variable RAM : RAMtype; + +begin + +process (clk_a) +begin +if rising_edge(clk_a) then + if en_a = '1' and we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + dout_a <= RAM(to_integer(addr_a)); +end if; +end process; + + +process (clk_b) +begin +if rising_edge(clk_b) then + if en_b = '1' and we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + dout_b <= RAM(to_integer(addr_b)); +end if; +end process; + +end Behavioral; +