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- fixed broken tx-interrupt

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- added tx_int and rx_int to status reg
- tx-int is acked by writing to ctrl reg
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git-svn-id: http://moon:8086/svn/vhdl/trunk@507 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-13 21:21:22 +00:00
parent 38b70b722c
commit 5b743dea38
1 changed files with 42 additions and 9 deletions
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lib/uart/uart_wb.vhd
+42 -9
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@@ -35,6 +35,8 @@ ARCHITECTURE behavior OF uart_wb IS
serial_out : out std_logic; serial_out : out std_logic;
buffer_full : out std_logic; buffer_full : out std_logic;
buffer_half_full : out std_logic; buffer_half_full : out std_logic;
tx_complete : out std_logic;
tx_empty : out std_logic;
clk : in std_logic clk : in std_logic
); );
END COMPONENT; END COMPONENT;
@@ -66,11 +68,17 @@ ARCHITECTURE behavior OF uart_wb IS
signal rx_data_present : std_logic; signal rx_data_present : std_logic;
signal rx_full : std_logic; signal rx_full : std_logic;
signal rx_half_full : std_logic; signal rx_half_full : std_logic;
signal uart_status_port : unsigned(7 downto 0); signal uart_status_port : unsigned(15 downto 0);
signal reg_uart_baud : unsigned(15 downto 0); signal reg_uart_baud : unsigned(15 downto 0);
signal rx_int_en : std_logic; signal rx_int_en : std_logic;
signal tx_int_en : std_logic; signal tx_int_en : std_logic;
signal irq_rx : std_logic;
signal irq_tx : std_logic;
signal irq_tx_ack : std_logic;
signal tx_complete : std_logic;
signal tx_empty : std_logic;
signal tx_busy : std_logic;
begin begin
SRDY_O <= CYC_I; SRDY_O <= CYC_I;
@@ -81,8 +89,9 @@ registers_write:
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
reg_we_uart_tx <= '0'; reg_we_uart_tx <= '0';
irq_tx_ack <= '0';
if RST_I = '1' then if RST_I = '1' then
reg_uart_baud <= to_unsigned(53, 8); reg_uart_baud <= to_unsigned(53, 16);
rx_int_en <= '0'; rx_int_en <= '0';
tx_int_en <= '0'; tx_int_en <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then elsif (STB_I and CYC_I and WE_I) = '1' then
@@ -90,12 +99,13 @@ registers_write:
when "0000" => when "0000" =>
reg_we_uart_tx <= '1'; reg_we_uart_tx <= '1';
reg_uart_tx <= DAT_I(7 downto 0); reg_uart_tx <= DAT_I(7 downto 0);
when "0001" => when "0001" =>
rx_int_en <= DAT_I(6); rx_int_en <= DAT_I(6);
tx_int_en <= DAT_I(5); tx_int_en <= DAT_I(5);
irq_tx_ack <= DAT_I(8);
when "0010" => when "0010" =>
reg_uart_baud <= DAT_I(15 downto 0); reg_uart_baud <= DAT_I(15 downto 0);
@@ -121,7 +131,7 @@ registers_read:
DAT_O(7 downto 0) <= unsigned(reg_uart_rx); DAT_O(7 downto 0) <= unsigned(reg_uart_rx);
when "0001" => when "0001" =>
DAT_O(7 downto 0) <= uart_status_port; DAT_O(15 downto 0) <= uart_status_port;
when "0010" => when "0010" =>
DAT_O(15 downto 0) <= reg_uart_baud; DAT_O(15 downto 0) <= reg_uart_baud;
@@ -148,6 +158,27 @@ baud_timer:
end if; end if;
end process; end process;
tx_interrupt:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
irq_tx <= '0';
tx_busy <= '0';
elsif irq_tx_ack = '1' then
irq_tx <= '0';
else
if tx_empty = '0' then
tx_busy <= '1';
elsif tx_busy = '1' then
irq_tx <= tx_int_en;
tx_busy <= '0';
end if;
end if;
irq_rx <= rx_data_present and rx_int_en;
end if;
end process;
inst_uart_tx: uart_tx inst_uart_tx: uart_tx
port map port map
( (
@@ -158,6 +189,8 @@ inst_uart_tx: uart_tx
serial_out => ser_tx, serial_out => ser_tx,
buffer_full => tx_full, buffer_full => tx_full,
buffer_half_full => tx_half_full, buffer_half_full => tx_half_full,
tx_complete => tx_complete,
tx_empty => tx_empty,
clk => CLK_I clk => CLK_I
); );
@@ -174,8 +207,8 @@ inst_uart_rx: uart_rx
buffer_half_full => rx_half_full, buffer_half_full => rx_half_full,
clk => CLK_I clk => CLK_I
); );
uart_status_port <= '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
INT_O <= (rx_data_present and rx_int_en) or (not tx_full and tx_int_en); INT_O <= irq_rx or irq_tx;
end behavior; end behavior;