diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo index c2c1137..bf718fb 100644 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo +++ b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo @@ -5,6 +5,7 @@ vcom -explicit -93 "../src/core/cpu_pkg.vhd" vcom -explicit -93 "../src/core/stack_ctrl.vhd" vcom -explicit -93 "../src/core/reg_dual.vhd" vcom -explicit -93 "../src/core/chipram.vhd" +vcom -explicit -93 "../src/core/chipreg.vhd" vcom -explicit -93 "../src/core/pc.vhd" vcom -explicit -93 "../src/core/dpath_ctrl.vhd" vcom -explicit -93 "../src/core/int_ctrl.vhd" diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo index f83b9b4..aba9eda 100644 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo +++ b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo @@ -12,8 +12,8 @@ vcom -explicit -93 "../src/core/dpath_ctrl.vhd" vcom -explicit -93 "../src/core/int_ctrl.vhd" vcom -explicit -93 "../src/core/alu.vhd" vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/irom_reti_issue.vhdl" -vcom -explicit -93 "../src/core/tb_cpu.vhd" +vcom -explicit -93 "../src/reti_issue_irom.vhdl" +vcom -explicit -93 "../src/tb_cpu_irq.vhd" vsim -t 1ps -lib work tb_cpu do {tb_cpu_reti_issue.wdo} view wave diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo index 1e67acb..d6d7e7e 100644 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo +++ b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo @@ -2,6 +2,16 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -format Literal /tb_cpu/uut/iphase add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines +add wave -noupdate -format Literal /tb_cpu/reg +add wave -noupdate -format Logic /tb_cpu/int_in +add wave -noupdate -format Logic /tb_cpu/int_ack +add wave -noupdate -format Literal /tb_cpu/xmem_din +add wave -noupdate -format Literal /tb_cpu/xmem_dout +add wave -noupdate -format Literal /tb_cpu/xmem_addr +add wave -noupdate -format Logic /tb_cpu/xmem_we +add wave -noupdate -format Logic /tb_cpu/xmem_re +add wave -noupdate -format Logic /tb_cpu/io_sel +add wave -noupdate -format Literal /tb_cpu/sram add wave -noupdate -divider {Chip RAM} add wave -noupdate -format Literal /tb_cpu/uut/iphase add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname @@ -24,9 +34,7 @@ add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out @@ -65,7 +73,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctr add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {8115990 ps} 0} +WaveRestoreCursors {{Cursor 1} {0 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -79,4 +87,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {8048536 ps} {8340629 ps} +WaveRestoreZoom {0 ps} {47421482 ps}