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[DE0-Nano]

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- added POR for CPU
- UART set to 460800 baud and added more FIFO depth

git-svn-id: http://moon:8086/svn/vhdl/trunk@1367 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-01-12 02:54:47 +00:00
parent 6e9407ef79
commit 5a2a217622
1 changed files with 30 additions and 15 deletions
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projects/mips_de0_nano/quartus/mips/mips_sys.vhd
+30 -15
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@@ -130,11 +130,12 @@ ARCHITECTURE behavior OF mips_sys IS
signal gpo0 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0) := (others => '0');
signal sys_rst : STD_LOGIC;
signal sys_nmi : STD_LOGIC;
signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR
signal sys_rst : STD_LOGIC := '1'; -- pre-init for POR
signal reset_counter : unsigned(7 downto 0) := (others => '1');
signal reset : STD_LOGIC := '1';
signal cpu_rst_count : unsigned(23 downto 0) := (others => '1'); -- pre-init for POR
signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR
subtype addr_t is unsigned (2 downto 0);
subtype reg_t is unsigned (7 downto 0);
@@ -148,7 +149,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal reg_we : STD_LOGIC;
BEGIN
sys_rst <= reset;
sys_nmi <= not sys_nmi_n;
sys_leds <= cpu_debug & gpo0(5 downto 0);
spi_ss_n <= not spi_ss;
@@ -182,17 +182,32 @@ inst_jtag_reg: entity work.jtag_reg
re_o => reg_re
);
power_up_reset:
sys_reset:
process(sys_clk)
begin
if rising_edge(sys_clk) then
if sys_rst_n = '0' then
reset <= '1';
reset_counter <= (others => '1');
elsif (reset_counter /= 0) then
reset_counter <= reset_counter - 1;
sys_rst <= '1';
sys_rst_count <= (others => '1');
elsif (sys_rst_count /= 0) then
sys_rst_count <= sys_rst_count - 1;
else
reset <= '0';
sys_rst <= '0';
end if;
end if;
end process;
cpu_reset:
process(sys_clk)
begin
if rising_edge(sys_clk) then
if sys_rst_n = '0' then
cpu_rst <= '1';
cpu_rst_count <= (others => '1');
elsif (cpu_rst_count /= 0) then
cpu_rst_count <= cpu_rst_count - 1;
else
cpu_rst <= '0';
end if;
end if;
end process;
@@ -284,7 +299,7 @@ inst_mips_top: entity work.mips_top
nmi => sys_nmi,
eb => '1',
cpu_clk => sys_clk,
RST_I => sys_rst,
RST_I => cpu_rst,
CLK_I => sys_clk,
ACK_I => ACK_I,
SRDY_I => SRDY_I,
@@ -344,8 +359,8 @@ inst_uart0 : entity work.uart_wb
GENERIC MAP
(
f_sysclk => F_SYSCLK,
baudrate_default => 115200.0,
fifo_depth_bits => 1
baudrate_default => 460800.0,
fifo_depth_bits => 4
)
PORT MAP
(
@@ -370,8 +385,8 @@ inst_uart1 : entity work.uart_wb
GENERIC MAP
(
f_sysclk => F_SYSCLK,
baudrate_default => 115200.0,
fifo_depth_bits => 1
baudrate_default => 460800.0,
fifo_depth_bits => 4
)
PORT MAP
(