From 5889dc2d4a50dcf4ba9a09a9eaa26ed969ce8c30 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 11 Feb 2010 21:56:03 +0000 Subject: [PATCH] - added new FIFO generics - no STB_O if Bus input FIFO full. => Bus out FIFO is read if SRDY_I = '1' and MRDY_O = '1' Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@748 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_bui.vhd | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd index 0a808a7..3835113 100644 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd @@ -193,7 +193,6 @@ architecture behavior of biu is signal write_fifo_we : std_logic; signal write_fifo_full : std_logic; signal write_fifo_empty : std_logic; - signal write_busy : std_logic; alias write_fifo_addr_in is write_fifo_din(31 downto 0); alias write_fifo_data_in is write_fifo_din(63 downto 32); @@ -229,7 +228,7 @@ read_cyc_register: WE_O <= bout_fifo_we_out; cpu_imem_rdy <= not icache_busy after 4.5 ns; - busy <= CYC_O_dmem_rd or dcache_busy or (write_busy); + busy <= CYC_O_dmem_rd or dcache_busy or (write_fifo_full); cpu_dmem_rdy <= not busy after 4.5 ns; inst_icache : icache @@ -287,14 +286,15 @@ inst_dcache : dcache dcached <= '1' when cpu_dmem_addr(31 downto 29) /= "101" else '0'; cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd; - dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_busy); + dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_fifo_full); -- Instantiate synchronous FIFO inst_bin_fifo: entity work.fifo_async GENERIC MAP ( - addr_width => 4, - data_width => 32 + addr_width => 4, + data_width => 32, + do_last_read_update => true ) PORT MAP ( @@ -321,8 +321,9 @@ inst_bin_fifo: entity work.fifo_async inst_bout_fifo: entity work.fifo_async GENERIC MAP ( - addr_width => 4, - data_width => 69 + addr_width => 4, + data_width => 69, + do_last_read_update => false ) PORT MAP ( @@ -339,7 +340,7 @@ inst_bout_fifo: entity work.fifo_async data_r => bout_fifo_dout ); bout_rdy <= not bout_fifo_full; - bout_fifo_re <= SRDY_I; + bout_fifo_re <= SRDY_I and not bin_fifo_full; bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache; @@ -360,7 +361,8 @@ inst_write_fifo: entity work.fifo_sync GENERIC MAP ( addr_width => 4, - data_width => 68 + data_width => 68, + do_last_read_update => true ) PORT MAP ( @@ -368,7 +370,7 @@ inst_write_fifo: entity work.fifo_sync clk => cpu_clk, we => write_fifo_we, re => write_fifo_re, - fifo_full => write_busy, + fifo_full => write_fifo_full, fifo_empty => write_fifo_empty, fifo_afull => open, fifo_aempty => open,