From 584ac47a8a66df32512d8c0aeb387d15580f9911 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 17 Oct 2009 12:58:28 +0000 Subject: [PATCH] - Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. Newlib's memcpy() (MIPS-optimized) uses this for unaligned copy. Consectutive load instructions without nops using same target register (which is legal) like lw $1, 0(mem) lwl $1, 1(mem) or lwl $1, 0(mem) lwr $1, 1(mem) or similar, lead to incorrect result. Now it's fixed. git-svn-id: http://moon:8086/svn/vhdl/trunk@519 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index cce6fdb..2cc39e8 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -744,7 +744,13 @@ proc_stage_MEM_n: MEM_stage.pa_off <= EX_stage.pa_off; MEM_stage.reg_wptr <= EX_stage.reg_wptr; MEM_stage.nop <= sdu.MEM_nop; - MEM_stage.ex_result <= EX_stage.reg_b; + if MEM_stage.reg_wptr = EX_stage.reg_wptr then + if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then + MEM_stage.ex_result <= MEM_stage.data; + end if; + else + MEM_stage.ex_result <= EX_stage.reg_b; + end if; if EX_stage.ctrl.cop_instr_en = '1' then if EX_stage.ctrl.cop_read = '1' then MEM_stage.ex_result <= cop_din;