diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index cce6fdb..2cc39e8 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -744,7 +744,13 @@ proc_stage_MEM_n:
 				MEM_stage.pa_off		<= EX_stage.pa_off;
 				MEM_stage.reg_wptr		<= EX_stage.reg_wptr;
 				MEM_stage.nop			<= sdu.MEM_nop;
-				MEM_stage.ex_result		<= EX_stage.reg_b;
+				if MEM_stage.reg_wptr = EX_stage.reg_wptr then
+					if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then
+						MEM_stage.ex_result	<= MEM_stage.data;
+					end if;
+				else
+					MEM_stage.ex_result		<= EX_stage.reg_b;
+				end if;
 				if EX_stage.ctrl.cop_instr_en = '1' then
 					if EX_stage.ctrl.cop_read = '1' then
 						MEM_stage.ex_result	<= cop_din;