diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
index bc4d2c8..ee69877 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
@@ -117,7 +117,6 @@ add wave -noupdate -divider I-Cache
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
 add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
@@ -148,6 +147,11 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/clk_a
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/clk_b
 add wave -noupdate -divider D-Cache
+add wave -noupdate -format Logic /tb_mips_top/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cyc_o_dmem_rd
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/uncached_access
 add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/ctrl
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
@@ -195,7 +199,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_cache_index
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_word_index
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {16285282 ps} 0}
+WaveRestoreCursors {{Cursor 1} {249927 ps} 0} {{Cursor 2} {3999904775 ps} 0}
 configure wave -namecolwidth 188
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -209,4 +213,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {16052883 ps} {16566606 ps}
+WaveRestoreZoom {0 ps} {553336 ps}