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CLOCKGEN: cpu_clock is now variable. SYS_CLK is fixed to input frequency

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git-svn-id: http://moon:8086/svn/vhdl/trunk@951 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-04-27 13:39:29 +00:00
parent da67d66447
commit 57f8626d86
4 changed files with 34 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/clockgen_virtex4.vhd
+14 -14
View File
@@ -34,8 +34,8 @@ entity clockgen is
generic generic
( (
clk_in_freq : real := 100.0; clk_in_freq : real := 100.0;
cpu_clk_out_freq : real := 100.0;
vga_clk_out_freq : real := 100.0; vga_clk_out_freq : real := 100.0;
sys_clk_out_freq : real := 100.0;
sdr0_clk_out_phaseshift : integer := 0; sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0 sdr1_clk_out_phaseshift : integer := 0
); );
@@ -63,9 +63,9 @@ architecture tech of clockgen is
signal vga_clkfx : std_logic; signal vga_clkfx : std_logic;
signal vga_clk0_bufg : std_logic; signal vga_clk0_bufg : std_logic;
signal sys_clk0 : std_logic; signal sys_clk0 : std_logic;
signal sys_clkfx : std_logic;
signal sys_clk0_bufg : std_logic; signal sys_clk0_bufg : std_logic;
signal sys_clkfx_bufg : std_logic; signal cpu_clkfx : std_logic;
signal cpu_clkfx_bufg : std_logic;
signal sdr0_clk0 : std_logic; signal sdr0_clk0 : std_logic;
signal sdr0_clk270 : std_logic; signal sdr0_clk270 : std_logic;
signal sdr1_clk0 : std_logic; signal sdr1_clk0 : std_logic;
@@ -141,13 +141,13 @@ BUFG_vga_clkfx : BUFG
); );
-- Compnent instantiation -- Compnent instantiation
inst_DCM_SYS_FX : DCM_BASE inst_DCM_CPU_FX : DCM_BASE
generic map generic map
( (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, sys_clk_out_freq), -- Can be any interger from 1 to 32 CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, sys_clk_out_freq), -- Can be any integer from 2 to 32 CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
@@ -171,7 +171,7 @@ BUFG_vga_clkfx : BUFG
CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => sys_clkfx, -- DCM CLK synthesis out (M/D) CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sys_fx_lock, -- DCM LOCK status output LOCKED => sys_fx_lock, -- DCM LOCK status output
CLKFB => sys_clk0_bufg, -- DCM clock feedback CLKFB => sys_clk0_bufg, -- DCM clock feedback
@@ -189,12 +189,12 @@ BUFG_sys_clk0 : BUFG
BUFG_sys_clkfx : BUFG BUFG_sys_clkfx : BUFG
port map port map
( (
O => sys_clkfx_bufg, -- Clock buffer output O => cpu_clkfx_bufg, -- Clock buffer output
I => sys_clkfx -- Clock buffer input I => cpu_clkfx -- Clock buffer input
); );
cpu_clk_out <= sys_clk0_bufg; sys_clk_out <= sys_clk0_bufg;
sys_clk_out <= sys_clkfx_bufg; cpu_clk_out <= cpu_clkfx_bufg;
inst_DCM_SDRCLK_0 : DCM_BASE inst_DCM_SDRCLK_0 : DCM_BASE
generic map generic map
@@ -204,7 +204,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -256,7 +256,7 @@ bufg_sdr0_clk270: bufg
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -343,7 +343,7 @@ dcm_reset2:
end process; end process;
reset_out_logic: reset_out_logic:
process(rst_in, clk_in) process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock)
begin begin
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
sys_rst_out <= '1'; sys_rst_out <= '1';
projects/mips_sys/src/mips_sys.vhd
+11 -11
View File
@@ -43,7 +43,7 @@ ENTITY mips_sys IS
GENERIC GENERIC
( (
sys_freq_in : real := 100.0; sys_freq_in : real := 100.0;
sys_freq : real := 100.0; cpu_freq : real := 100.0;
sdram_phaseshift : integer := 0; sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60 tsvga : vga_timespec_t := ts_vga_800_600_60
@@ -211,7 +211,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb COMPONENT async_port_wb
GENERIC GENERIC
( (
f_sysclk : real := sys_freq; f_sysclk : real := sys_freq_in;
addr_width : natural := 32; addr_width : natural := 32;
data_width : natural := 32; data_width : natural := 32;
byte_sel_width : natural := 4; byte_sel_width : natural := 4;
@@ -266,7 +266,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT gpio_wb COMPONENT gpio_wb
Generic Generic
( (
f_sysclk : real := sys_freq f_sysclk : real := sys_freq_in
); );
PORT PORT
( (
@@ -777,7 +777,7 @@ inst_lcd_port: lcd_port
inst_gpio_wb : gpio_wb inst_gpio_wb : gpio_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq f_sysclk => sys_freq_in
) )
PORT MAP PORT MAP
( (
@@ -802,7 +802,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : async_port_wb inst_flash_port : async_port_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq, f_sysclk => sys_freq_in,
addr_width => 25, addr_width => 25,
data_width => 32, data_width => 32,
byte_sel_width => 1, byte_sel_width => 1,
@@ -835,7 +835,7 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb inst_usb_port : async_port_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq, f_sysclk => sys_freq_in,
addr_width => 4, addr_width => 4,
data_width => 16, data_width => 16,
byte_sel_width => 1, byte_sel_width => 1,
@@ -910,7 +910,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP GENERIC MAP
( (
clk_in_freq => sys_freq_in, clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq, cpu_clk_out_freq => cpu_freq,
vga_clk_out_freq => vga_freq, vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0, sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0 sdr1_clk_out_phaseshift => 0
@@ -935,8 +935,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP GENERIC MAP
( (
BL => BURST_LEN, BL => BURST_LEN,
f_sysclk => sys_freq, f_sysclk => sys_freq_in,
f_sdrclk => sys_freq, f_sdrclk => sys_freq_in,
fifo_depth => 5 fifo_depth => 5
) )
PORT MAP PORT MAP
@@ -1058,7 +1058,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb_0: entity work.ps2_wb inst_ps2_wb_0: entity work.ps2_wb
GENERIC MAP GENERIC MAP
( (
f_sys_clk => sys_freq f_sys_clk => sys_freq_in
) )
PORT MAP PORT MAP
( (
@@ -1097,7 +1097,7 @@ inst_ps2_phy_0: entity work.ps2_phy
inst_ps2_wb_1: entity work.ps2_wb inst_ps2_wb_1: entity work.ps2_wb
GENERIC MAP GENERIC MAP
( (
f_sys_clk => sys_freq f_sys_clk => sys_freq_in
) )
PORT MAP PORT MAP
( (
projects/mips_sys/src/mips_sys_sim.vhd
+8 -8
View File
@@ -43,7 +43,7 @@ ENTITY mips_sys IS
GENERIC GENERIC
( (
sys_freq_in : real := 100.0; sys_freq_in : real := 100.0;
sys_freq : real := 100.0; cpu_freq : real := 100.0;
sdram_phaseshift : integer := 0; sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_72 tsvga : vga_timespec_t := ts_vga_800_600_72
@@ -622,7 +622,7 @@ inst_lcd_port: entity work.lcd_port
inst_gpio_wb : entity work.gpio_wb inst_gpio_wb : entity work.gpio_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq f_sysclk => sys_freq_in
) )
PORT MAP PORT MAP
( (
@@ -647,7 +647,7 @@ inst_gpio_wb : entity work.gpio_wb
inst_flash_port : entity work.flash_port_wb inst_flash_port : entity work.flash_port_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq, f_sysclk => sys_freq_in,
addr_width => 25, addr_width => 25,
data_width => 32, data_width => 32,
async_timespec => ts_flash async_timespec => ts_flash
@@ -680,7 +680,7 @@ inst_flash_port : entity work.flash_port_wb
inst_usb_port : entity work.async_port_wb inst_usb_port : entity work.async_port_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq, f_sysclk => sys_freq_in,
addr_width => 2, addr_width => 2,
data_width => 16, data_width => 16,
byte_sel_width => 1, byte_sel_width => 1,
@@ -828,7 +828,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP GENERIC MAP
( (
clk_in_freq => sys_freq_in, clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq, cpu_clk_out_freq => cpu_freq,
vga_clk_out_freq => vga_freq, vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0, sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0 sdr1_clk_out_phaseshift => 0
@@ -854,8 +854,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP GENERIC MAP
( (
BL => BURST_LEN, BL => BURST_LEN,
f_sysclk => sys_freq, f_sysclk => sys_freq_in,
f_sdrclk => sys_freq, f_sdrclk => sys_freq_in,
fifo_depth => 5 fifo_depth => 5
) )
PORT MAP PORT MAP
@@ -976,7 +976,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb: entity work.ps2_wb inst_ps2_wb: entity work.ps2_wb
GENERIC MAP GENERIC MAP
( (
f_sys_clk => sys_freq f_sys_clk => sys_freq_in
) )
PORT MAP PORT MAP
( (
projects/mips_sys/src/tb_mips_sys.vhd
+1 -1
View File
@@ -146,7 +146,7 @@ uut: entity work.mips_sys
GENERIC MAP GENERIC MAP
( (
sys_freq_in => 100.000, sys_freq_in => 100.000,
sys_freq => 100.000, cpu_freq => 100.000,
sdram_phaseshift => 0, sdram_phaseshift => 0,
tsvga => ts_vga_800_600_72 tsvga => ts_vga_800_600_72
) )