CLOCKGEN: cpu_clock is now variable. SYS_CLK is fixed to input frequency

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git-svn-id: http://moon:8086/svn/vhdl/trunk@951 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_sys/src/mips_sys_sim.vhd

@@ -43,7 +43,7 @@ ENTITY mips_sys IS
 GENERIC
 (
 	sys_freq_in			: real		    	:= 100.0;
-	sys_freq			: real				:= 100.0;
+	cpu_freq			: real				:= 100.0;
 	sdram_phaseshift	: integer			:= 0;
 	tsvga				: vga_timespec_t 	:= ts_vga_800_600_72
 
@@ -622,7 +622,7 @@ inst_lcd_port: entity work.lcd_port
 inst_gpio_wb : entity work.gpio_wb
 	GENERIC MAP
 	(
-		f_sysclk	=> sys_freq
+		f_sysclk	=> sys_freq_in
 	)
 	PORT MAP
 	(
@@ -647,7 +647,7 @@ inst_gpio_wb : entity work.gpio_wb
 inst_flash_port : entity work.flash_port_wb
 	GENERIC MAP
 	(
-		f_sysclk		=> sys_freq,
+		f_sysclk		=> sys_freq_in,
 		addr_width		=> 25,
 		data_width		=> 32,
 		async_timespec	=> ts_flash
@@ -680,7 +680,7 @@ inst_flash_port : entity work.flash_port_wb
 inst_usb_port : entity work.async_port_wb
 	GENERIC MAP
 	(
-		f_sysclk		=> sys_freq,
+		f_sysclk		=> sys_freq_in,
 		addr_width		=> 2,
 		data_width		=> 16,
 		byte_sel_width	=> 1,
@@ -828,7 +828,7 @@ inst_clockgen : entity work.clockgen
 	GENERIC MAP
 	(
 		clk_in_freq				=> sys_freq_in,
-		sys_clk_out_freq		=> sys_freq,
+		cpu_clk_out_freq		=> cpu_freq,
 		vga_clk_out_freq		=> vga_freq,
 		sdr0_clk_out_phaseshift	=> 0,
 		sdr1_clk_out_phaseshift	=> 0
@@ -854,8 +854,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
 	GENERIC MAP
 	(
 		BL				=> BURST_LEN,
-		f_sysclk		=> sys_freq,
-		f_sdrclk		=> sys_freq,
+		f_sysclk		=> sys_freq_in,
+		f_sdrclk		=> sys_freq_in,
 		fifo_depth		=> 5
 	)
 	PORT MAP
@@ -976,7 +976,7 @@ inst_ac97_wb : entity work.ac97_wb
 inst_ps2_wb: entity work.ps2_wb
 	GENERIC MAP
 	(
-		f_sys_clk	=> sys_freq
+		f_sys_clk	=> sys_freq_in
 	)
 	PORT MAP
 	(