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CLOCKGEN: cpu_clock is now variable. SYS_CLK is fixed to input frequency

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git-svn-id: http://moon:8086/svn/vhdl/trunk@951 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-04-27 13:39:29 +00:00
parent da67d66447
commit 57f8626d86
4 changed files with 34 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys.vhd
+11 -11
View File
@@ -43,7 +43,7 @@ ENTITY mips_sys IS
GENERIC
(
sys_freq_in : real := 100.0;
sys_freq : real := 100.0;
cpu_freq : real := 100.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60
@@ -211,7 +211,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk : real := sys_freq;
f_sysclk : real := sys_freq_in;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
@@ -266,7 +266,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT gpio_wb
Generic
(
f_sysclk : real := sys_freq
f_sysclk : real := sys_freq_in
);
PORT
(
@@ -777,7 +777,7 @@ inst_lcd_port: lcd_port
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
f_sysclk => sys_freq_in
)
PORT MAP
(
@@ -802,7 +802,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
f_sysclk => sys_freq_in,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
@@ -835,7 +835,7 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
f_sysclk => sys_freq_in,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
@@ -910,7 +910,7 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
cpu_clk_out_freq => cpu_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
@@ -935,8 +935,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => sys_freq,
f_sdrclk => sys_freq,
f_sysclk => sys_freq_in,
f_sdrclk => sys_freq_in,
fifo_depth => 5
)
PORT MAP
@@ -1058,7 +1058,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb_0: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
f_sys_clk => sys_freq_in
)
PORT MAP
(
@@ -1097,7 +1097,7 @@ inst_ps2_phy_0: entity work.ps2_phy
inst_ps2_wb_1: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
f_sys_clk => sys_freq_in
)
PORT MAP
(