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CLOCKGEN: cpu_clock is now variable. SYS_CLK is fixed to input frequency

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git-svn-id: http://moon:8086/svn/vhdl/trunk@951 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-04-27 13:39:29 +00:00
parent da67d66447
commit 57f8626d86
4 changed files with 34 additions and 34 deletions
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projects/mips_sys/src/clockgen_virtex4.vhd
+14 -14
View File
@@ -34,8 +34,8 @@ entity clockgen is
generic
(
clk_in_freq : real := 100.0;
cpu_clk_out_freq : real := 100.0;
vga_clk_out_freq : real := 100.0;
sys_clk_out_freq : real := 100.0;
sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0
);
@@ -63,9 +63,9 @@ architecture tech of clockgen is
signal vga_clkfx : std_logic;
signal vga_clk0_bufg : std_logic;
signal sys_clk0 : std_logic;
signal sys_clkfx : std_logic;
signal sys_clk0_bufg : std_logic;
signal sys_clkfx_bufg : std_logic;
signal cpu_clkfx : std_logic;
signal cpu_clkfx_bufg : std_logic;
signal sdr0_clk0 : std_logic;
signal sdr0_clk270 : std_logic;
signal sdr1_clk0 : std_logic;
@@ -141,13 +141,13 @@ BUFG_vga_clkfx : BUFG
);
-- Compnent instantiation
inst_DCM_SYS_FX : DCM_BASE
inst_DCM_CPU_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, sys_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, sys_clk_out_freq), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
@@ -171,7 +171,7 @@ BUFG_vga_clkfx : BUFG
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => sys_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sys_fx_lock, -- DCM LOCK status output
CLKFB => sys_clk0_bufg, -- DCM clock feedback
@@ -189,12 +189,12 @@ BUFG_sys_clk0 : BUFG
BUFG_sys_clkfx : BUFG
port map
(
O => sys_clkfx_bufg, -- Clock buffer output
I => sys_clkfx -- Clock buffer input
O => cpu_clkfx_bufg, -- Clock buffer output
I => cpu_clkfx -- Clock buffer input
);
cpu_clk_out <= sys_clk0_bufg;
sys_clk_out <= sys_clkfx_bufg;
sys_clk_out <= sys_clk0_bufg;
cpu_clk_out <= cpu_clkfx_bufg;
inst_DCM_SDRCLK_0 : DCM_BASE
generic map
@@ -204,7 +204,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -256,7 +256,7 @@ bufg_sdr0_clk270: bufg
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -343,7 +343,7 @@ dcm_reset2:
end process;
reset_out_logic:
process(rst_in, clk_in)
process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock)
begin
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
sys_rst_out <= '1';