From 57c876c27a5f11101fb0a09db6401dfda63a4047 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 23 Jul 2014 20:06:08 +0000 Subject: [PATCH] - unversion git-svn-id: http://moon:8086/svn/vhdl/trunk@1044 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/tools/flashgen.exe | Bin 12196 -> 0 bytes lib/CPUs/MIPS/tools/flashgen_big.exe | Bin 12301 -> 0 bytes lib/CPUs/MIPS/tools/flashgen_little.exe | Bin 12301 -> 0 bytes lib/CPUs/MIPS/tools/ramgen.exe | Bin 22930 -> 0 bytes lib/CPUs/MIPS/tools/romgen.exe | Bin 21906 -> 0 bytes lib/CPUs/MIPS/tools/src/flashgen.c | 280 ++++---- lib/CPUs/MIPS/tools/src/ramgen.c | 764 ++++++++++----------- lib/CPUs/MIPS/tools/src/romgen.c | 856 ++++++++++++------------ 8 files changed, 950 insertions(+), 950 deletions(-) delete mode 100644 lib/CPUs/MIPS/tools/flashgen.exe delete mode 100644 lib/CPUs/MIPS/tools/flashgen_big.exe delete mode 100644 lib/CPUs/MIPS/tools/flashgen_little.exe delete mode 100644 lib/CPUs/MIPS/tools/ramgen.exe delete mode 100644 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zM?l$cP&7DwjJ($vFH|Y3z$3E)%t7%=h3E59pH1K~*B@#X1LY*HxS%r{e@UZ^8dfEq zELB37so`gdVw3(w#$%lq-vEV7WVSj8ipS=MW1zeU9%{_T;uLOA*eJgM<${g!Dk$I>@>N%>XKfTszV4Dw571gsegYo*ns5;mnO$&eypJB< z7}lUx^FcX}E0!d&QenOqC(r`Z)#AC622Ky zH1QIV-WlR$q@|=qQ$0PYWMGA&#Zp>2tM}rP(dq4@rls}x(iOED{taI)-lKCe*3yiD zm(J*<&Qd3##!2uw38aRG?=8ZO>qA;|YpAVZBR zdm^7mWiRwOFs!=ueGn_4Q%YCRzcgqGfDClG&hxGun!WZiEm?*r`$Fh|;pLpbTh|c^axu(I&F)JH}k1>bn<1tFtZ=-}EoS -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define SDRAM_BASE 0x40000000 -#define FLASH_OFFSET 0x00000000 - -#define MAGIC_EB 0x4A464931 // "JFI1" in big-endian; -#define MAGIC_EL 0x3149464A // "JFI1" in little-endian; - -UINT32 conv_endian32(UINT32 src) -{ - UINT32 dst; - - dst = (0xFF000000 & (src << 24)) - | (0x00FF0000 & (src << 8)) - | (0x0000FF00 & (src >> 8)) - | (0x000000FF & (src >> 24)); - - return dst; -}; - -// -------------------------------------------------------------- -typedef struct _sflash_img_hdr_t -{ - UINT32 magic; - UINT32 target_addr; - UINT32 img_offset; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -// -------------------------------------------------------------- -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_flash[1024]; - char name_prj[1024]; - char *pBuf; - UINT32 *pBuf32; - flash_img_hdr_t img_hdr = {0}; - - FILE *pFile; - int filesize; - long start, end; - int i; - - if (argc < 2) - { - fprintf(stderr, "Usage: flashgen [-{EL|EB}]\n"); - return 1; - } - - pFilenameIn = argv[1]; - pFile = fopen(pFilenameIn, "rb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_flash, "%s.flash.bin", name_prj); - - // determine filesize - fseek(pFile, 0, SEEK_SET); - start = ftell(pFile); - fseek(pFile, 0, SEEK_END); - end = ftell(pFile); - fseek(pFile, 0, SEEK_SET); - filesize = (end-start); - - pBuf = (char*)malloc(filesize); - fread(pBuf, 1, filesize, pFile); - - fclose(pFile); - - pFile = fopen(name_flash, "wb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", name_flash); - return 1; - } - - img_hdr.magic = MAGIC_EL; - img_hdr.target_addr = SDRAM_BASE; - img_hdr.img_size = filesize; - img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = FLASH_OFFSET; - - if (argc == 3) - { - if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B')) - { - img_hdr.magic = MAGIC_EB; - pBuf32 = (UINT32*)pBuf; - for (i=0; i < filesize/4; i ++) - pBuf32[i] = conv_endian32(pBuf32[i]); - } - } - fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile); - fwrite(pBuf, 1, filesize, pFile); - - fclose(pFile); - - return 0; -} - +#include +#include +#include +#include + +#define INT8 char +#define INT16 short +#define INT32 long +#define UINT8 unsigned char +#define UINT16 unsigned short +#define UINT32 unsigned long +#define INT int +#define UINT unsigned int +#define FLOAT32 float +#define FLOAT64 double + +#define SDRAM_BASE 0x40000000 +#define FLASH_OFFSET 0x00000000 + +#define MAGIC_EB 0x4A464931 // "JFI1" in big-endian; +#define MAGIC_EL 0x3149464A // "JFI1" in little-endian; + +UINT32 conv_endian32(UINT32 src) +{ + UINT32 dst; + + dst = (0xFF000000 & (src << 24)) + | (0x00FF0000 & (src << 8)) + | (0x0000FF00 & (src >> 8)) + | (0x000000FF & (src >> 24)); + + return dst; +}; + +// -------------------------------------------------------------- +typedef struct _sflash_img_hdr_t +{ + UINT32 magic; + UINT32 target_addr; + UINT32 img_offset; + UINT32 img_size; + UINT32 hdr_next; + UINT8 img_name[128]; + UINT8 res[108]; + +} flash_img_hdr_t; + +// -------------------------------------------------------------- +void basename(char *pSrc, char *pDst) +{ + int i, size; + + size = strlen(pSrc); + + while(pSrc[size] != '.') + size--; + + for (i=0; i < size; i++) + pDst[i] = pSrc[i]; + + pDst[i] = 0; + +} + +// -------------------------------------------------------------- +int main(int argc, char *argv[]) +{ + char *pFilenameIn; + char name_flash[1024]; + char name_prj[1024]; + char *pBuf; + UINT32 *pBuf32; + flash_img_hdr_t img_hdr = {0}; + + FILE *pFile; + int filesize; + long start, end; + int i; + + if (argc < 2) + { + fprintf(stderr, "Usage: flashgen [-{EL|EB}]\n"); + return 1; + } + + pFilenameIn = argv[1]; + pFile = fopen(pFilenameIn, "rb"); + if (!pFile) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + basename(pFilenameIn, name_prj); + sprintf(name_flash, "%s.flash.bin", name_prj); + + // determine filesize + fseek(pFile, 0, SEEK_SET); + start = ftell(pFile); + fseek(pFile, 0, SEEK_END); + end = ftell(pFile); + fseek(pFile, 0, SEEK_SET); + filesize = (end-start); + + pBuf = (char*)malloc(filesize); + fread(pBuf, 1, filesize, pFile); + + fclose(pFile); + + pFile = fopen(name_flash, "wb"); + if (!pFile) + { + fprintf(stderr, "Error opening file %s\n", name_flash); + return 1; + } + + img_hdr.magic = MAGIC_EL; + img_hdr.target_addr = SDRAM_BASE; + img_hdr.img_size = filesize; + img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t); + img_hdr.hdr_next = FLASH_OFFSET; + + if (argc == 3) + { + if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B')) + { + img_hdr.magic = MAGIC_EB; + pBuf32 = (UINT32*)pBuf; + for (i=0; i < filesize/4; i ++) + pBuf32[i] = conv_endian32(pBuf32[i]); + } + } + fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile); + fwrite(pBuf, 1, filesize, pFile); + + fclose(pFile); + + return 0; +} + diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c index 8f61118..f2bf017 100644 --- a/lib/CPUs/MIPS/tools/src/ramgen.c +++ b/lib/CPUs/MIPS/tools/src/ramgen.c @@ -1,385 +1,385 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); - fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ +#include +#include +#include +#include + +#define ARCH_NAME "data" +#define ENT_NAME "ram" +#define JTAG_ADDR_WIDTH 16 + +// -------------------------------------------------------------- +void basename(char *pSrc, char *pDst) +{ + int i, size; + + size = strlen(pSrc); + + while(pSrc[size] != '.') + size--; + + for (i=0; i < size; i++) + pDst[i] = pSrc[i]; + + pDst[i] = 0; + +} + +int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "begin\n", ARCH_NAME); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); + fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + + return 0; +} + +int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "library UNISIM;\n"); + fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); + fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); + fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); + fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "begin\n", ARCH_NAME); + + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "\n"); + fputs(tpl, pFileOut); + + fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); + fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\telse\n"); + fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + return 0; +} + +int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, word_addr, filesize, romsize; + char binstr_addr[33]; + char binstr_data[33]; + + char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fputs(tpl, pFileOut); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); + fprintf(pFileOut, "# ---------------------------------------------------------------\n"); + fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); + fprintf(pFileOut, "# User 2\n"); + fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); + + word_addr = 0; + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); + word_addr++; + } + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); + fprintf(pFileOut, "exit\n"); + + return 0; +} + +int main(int argc, char *argv[]) +{ char *pFilenameIn; char name_prj[1024]; - char name_rom_tcl[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: ramgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); -// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} + char name_rom_tcl[1024]; + char name_rom[1024]; + char name_rom_v4ld[1024]; + FILE *pFileIn; + int filesize, romsize, nbits_addr, nbits_data; + long start, end; + int word, i; + + if (argc < 2) + { + fprintf(stderr, "Usage: ramgen \n"); + return 1; + } + + pFilenameIn = argv[1]; + if (argc == 3) + nbits_addr = atoi(argv[2]); + + + basename(pFilenameIn, name_prj); + sprintf(name_rom, "%s.vhd", name_prj); + sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); + sprintf(name_rom_tcl, "%s.tcl", name_prj); + + SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); +// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); + SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); + + + return 0; +} + diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c index f674a6a..e1a073e 100644 --- a/lib/CPUs/MIPS/tools/src/romgen.c +++ b/lib/CPUs/MIPS/tools/src/romgen.c @@ -1,428 +1,428 @@ -#include -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define ARCH_NAME "data" -#define ENT_NAME "rom" -#define JTAG_ADDR_WIDTH 16 - -UINT32 g_endianess_EB; - -// -------------------------------------------------------------- -UINT32 conv_endian32(UINT32 src) -{ - UINT32 dst; - - dst = (0xFF000000 & (src << 24)) - | (0x00FF0000 & (src << 8)) - | (0x0000FF00 & (src >> 8)) - | (0x000000FF & (src >> 24)); - - return dst; -}; - -UINT32 to_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -UINT32 from_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); - else - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); - else - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = - {"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word)); - else - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen [-{EL|EB}]\n"); - return 1; - } - - pFilenameIn = argv[1]; - nbits_addr = atoi(argv[2]); - - g_endianess_EB = 0; - if (argc == 4) - { - if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B')) - g_endianess_EB = 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - +#include +#include +#include +#include + +#define INT8 char +#define INT16 short +#define INT32 long +#define UINT8 unsigned char +#define UINT16 unsigned short +#define UINT32 unsigned long +#define INT int +#define UINT unsigned int +#define FLOAT32 float +#define FLOAT64 double + +#define ARCH_NAME "data" +#define ENT_NAME "rom" +#define JTAG_ADDR_WIDTH 16 + +UINT32 g_endianess_EB; + +// -------------------------------------------------------------- +UINT32 conv_endian32(UINT32 src) +{ + UINT32 dst; + + dst = (0xFF000000 & (src << 24)) + | (0x00FF0000 & (src << 8)) + | (0x0000FF00 & (src >> 8)) + | (0x000000FF & (src >> 24)); + + return dst; +}; + +UINT32 to_big_endian32(UINT32 src) +{ +#ifndef NATIVE_IS_BIG_ENDIAN + return conv_endian32(src); +#else + return src; +#endif +} + +UINT32 from_big_endian32(UINT32 src) +{ +#ifndef NATIVE_IS_BIG_ENDIAN + return conv_endian32(src); +#else + return src; +#endif +} + +void basename(char *pSrc, char *pDst) +{ + int i, size; + + size = strlen(pSrc); + + while(pSrc[size] != '.') + size--; + + for (i=0; i < size; i++) + pDst[i] = pSrc[i]; + + pDst[i] = 0; + +} + +int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + if (g_endianess_EB) + fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); + else + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "begin\n", ARCH_NAME); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + + return 0; +} + +int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "library UNISIM;\n"); + fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); + fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); + fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); + fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + if (g_endianess_EB) + fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); + else + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "begin\n", ARCH_NAME); + + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "\n"); + fputs(tpl, pFileOut); + + fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); + fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\telse\n"); + fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + return 0; +} + +int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, word_addr, filesize, romsize; + char binstr_addr[33]; + char binstr_data[33]; + + char tpl[] = + {"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fputs(tpl, pFileOut); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); + fprintf(pFileOut, "# ---------------------------------------------------------------\n"); + fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); + fprintf(pFileOut, "# User 1\n"); + fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); + + word_addr = 0; + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + if (g_endianess_EB) + fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word)); + else + fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); + word_addr++; + } + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); + fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); + fprintf(pFileOut, "exit\n"); + + return 0; +} + +int main(int argc, char *argv[]) +{ + char *pFilenameIn; + char name_prj[1024]; + char name_rom[1024]; + char name_rom_v4ld[1024]; + char name_rom_tcl[1024]; + + FILE *pFileIn; + int filesize, romsize, nbits_addr, nbits_data; + long start, end; + int word, i; + + if (argc < 2) + { + fprintf(stderr, "Usage: romgen [-{EL|EB}]\n"); + return 1; + } + + pFilenameIn = argv[1]; + nbits_addr = atoi(argv[2]); + + g_endianess_EB = 0; + if (argc == 4) + { + if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B')) + g_endianess_EB = 1; + } + + basename(pFilenameIn, name_prj); + sprintf(name_rom, "%s.vhd", name_prj); + sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); + sprintf(name_rom_tcl, "%s.tcl", name_prj); + + SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); + SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); + SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); + + + return 0; +} +