- removed module reset_virtex4

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git-svn-id: http://moon:8086/svn/vhdl/trunk@710 cc03376c-175c-47c8-b038-4cd826a8556b

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo

@@ -13,7 +13,6 @@ vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"
 vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
 vcom -explicit  -93 "../src/sdram_cmd.vhd"
 vcom -explicit  -93 "../src/sdram_ctrl.vhd"
 vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo

@@ -13,7 +13,6 @@ vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
 vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
 vcom -explicit  -93 "../src/sdram_config.vhd"
 vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
 vcom -explicit  -93 "../src/sdram_cmd.vhd"
 vcom -explicit  -93 "../src/sdram_ctrl.vhd"
 vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"

lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd

@@ -1,111 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Reset generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity reset is
-	port
-	(
-		clk			: in std_logic;
-		rst_in		: in std_logic;
-		rst_out		: out std_logic
-	);
-end;
-
-architecture tech of reset is
-   
-	signal rst : std_logic;
-	signal shift_pipe : std_logic_vector(3 downto 0);
-	attribute KEEP : string;
-	attribute KEEP of shift_pipe	: signal is "TRUE";
-
-begin
-   
-	rst <= shift_pipe(0);
-
-bufg_reset: bufg
-	port map
-	(
-		o  => rst_out,  
-		i  => rst
-	);
-	
-fdp0: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map 
-	(
-		d		=> rst_in,
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(3)
-	);
-
-fdp1: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map
-	(
-
-		d		=> shift_pipe(3),
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(2)
-	);
-
-fdp2: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map
-	(
-		d		=> shift_pipe(2),
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(1)
-	);
-
-fdp3: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map
-	(
-
-		d		=> shift_pipe(1),
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(0)
-	);
-  
-end tech;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd

@@ -91,7 +91,6 @@ architecture rtl of sdram_ctrl_top is
 
 	-- Clock generator
 
-	signal ctrl_rst			: std_logic;  
 	signal part_ctrl		: part_ctrl_t;  
 
 	-- SD command FIFO
@@ -128,14 +127,7 @@ begin
 	sd_cmd			<= sdr_cmd_t(to_integer(sd_cmd_fifo_out));
 
 	---------------------------------
-	inst_reset: entity work.reset
-	port map
-	(
-		clk					=> sys_clk_in,
-		rst_in				=> sys_rst_in,
-		rst_out				=> ctrl_rst
-	);
-	
+
 	-- Main controller
 	inst_sdram_ctrl : entity work.sdram_ctrl
 	Generic map 
@@ -145,7 +137,7 @@ begin
 	)
 	Port map 
 	(
-		rst				=> ctrl_rst,
+		rst				=> sys_rst_in,
 		clk				=> sys_clk_in,
 		u_busy			=> u_busy,
 		u_tag_in		=> u_tag_in,
@@ -170,7 +162,7 @@ begin
 	)
 	PORT MAP
 	(
-		rst			=>	ctrl_rst,
+		rst			=>	sys_rst_in,
 		clk_w		=>	sys_clk_in,
 		clk_r		=>	sdram_clk0_in,
 		we			=>	cmd_fifo_we,
@@ -191,7 +183,7 @@ begin
 	)
 	Port map
 	(
-		rst				=> ctrl_rst,
+		rst				=> sys_rst_in,
 		clk				=> sdram_clk0_in,
 		u_tag_in		=> sd_tag_fifo_out,
 		u_tag_out		=> u_tag,
@@ -211,7 +203,7 @@ begin
 	inst_ddr_phy : entity work.ddr_phy
 	Port map
 	(
-		sys_rst			=> ctrl_rst,
+		sys_rst			=> sys_rst_in,
 		sys_clk0		=> sdram_clk0_in,
 		sys_clk270		=> sdram_clk270_in,
 		u_tag_in		=> u_tag,