From 5694dddd9f16138c08a99d9d1dda9f1fdd672670 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 12 Oct 2008 11:02:41 +0000 Subject: [PATCH] - Changed we to be - Changed r_wn to we git-svn-id: http://moon:8086/svn/vhdl/trunk@50 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_bui.vhd | 18 +++++++++--------- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 8 ++++---- lib/CPUs/MIPS/src/core/mips_top.vhd | 16 ++++++++-------- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd index 3045fe3..f6b6690 100644 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd @@ -51,8 +51,8 @@ entity bui is cpu_dmem_err : out STD_LOGIC; cpu_dmem_rdy : out STD_LOGIC; cpu_dmem_en : in STD_LOGIC; - cpu_dmem_re : in STD_LOGIC; - cpu_dmem_we : in unsigned(3 downto 0); + cpu_dmem_we : in STD_LOGIC; + cpu_dmem_be : in unsigned(3 downto 0); cpu_dmem_dout : in word_t; cpu_dmem_din : out word_t; cpu_dmem_addr : in word_t @@ -103,8 +103,8 @@ architecture behavior of bui is CYC_O : out STD_LOGIC; en : in STD_LOGIC; cpu_en : in STD_LOGIC; - cpu_r_wn : in STD_LOGIC; - cpu_we : in unsigned(3 downto 0); + cpu_we : in STD_LOGIC; + cpu_be : in unsigned(3 downto 0); cpu_addr : in word_t; cpu_din : in word_t; cpu_dout : out word_t; @@ -117,7 +117,7 @@ architecture behavior of bui is signal s, sn : bus_state_t; signal bus_idle : std_logic; signal busy : std_logic; - signal dmem_we : unsigned(3 downto 0); + signal dmem_be : unsigned(3 downto 0); signal dcache_dout : word_t; signal dcache_mem_gnt : std_logic; signal icache_mem_gnt : std_logic; @@ -240,8 +240,8 @@ inst_dcache : dcache SRDY_I => SRDY_I_dcache, en => dcached, cpu_en => dcache_en, - cpu_r_wn => cpu_dmem_re, cpu_we => cpu_dmem_we, + cpu_be => cpu_dmem_be, cpu_addr => cpu_dmem_addr, cpu_din => cpu_dmem_dout, cpu_dout => dcache_dout, @@ -323,9 +323,9 @@ inst_write_fifo: entity work.fifo_sync write_fifo_data_in <= cpu_dmem_dout; write_fifo_addr_in <= cpu_dmem_addr; - write_fifo_sel_in <= cpu_dmem_we; + write_fifo_sel_in <= cpu_dmem_be; write_fifo_re <= STB_O_dmem_wr; - write_fifo_we <= cpu_dmem_en and not busy and not cpu_dmem_re; + write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we; dmem_rd_flags: process(CLK_I) @@ -339,7 +339,7 @@ dmem_rd_flags: uncached_access <= '1'; CYC_O_dmem_rd <= '0'; end if; - if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_re = '1' then + if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then if dcached = '0' then CYC_O_dmem_rd <= '1'; end if; diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 6c11e27..00080b4 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -43,8 +43,8 @@ entity pipeline is dmem_err : in STD_LOGIC; dmem_rdy : in STD_LOGIC; dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); + dmem_we : out STD_LOGIC; + dmem_be : out unsigned(3 downto 0); dmem_addr : out word_t; dmem_din : in word_t; dmem_dout : out word_t @@ -625,8 +625,8 @@ proc_stage_DMEM_ADDR: end if; end if; end process; - dmem_we <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns; - dmem_re <= not EX_stage.ctrl.dmem_we; + dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns; + dmem_we <= EX_stage.ctrl.dmem_we; dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; dmem_addr <= EX_stage.va; cop_din <= EX_stage.reg_b; diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd index 7741e64..05959dd 100644 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ b/lib/CPUs/MIPS/src/core/mips_top.vhd @@ -66,8 +66,8 @@ architecture rtl of mips_top is dmem_err : in STD_LOGIC; dmem_rdy : in STD_LOGIC; dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); + dmem_we : out STD_LOGIC; + dmem_be : out unsigned(3 downto 0); dmem_addr : out word_t; dmem_din : in word_t; dmem_dout : out word_t @@ -81,11 +81,11 @@ architecture rtl of mips_top is signal dmem_err : std_logic; signal dmem_rdy : std_logic; signal dmem_en : std_logic; - signal dmem_re : std_logic; + signal dmem_we : std_logic; signal dmem_addr : word_t; signal dmem_dout : word_t; signal dmem_din : word_t; - signal dmem_we : unsigned(3 downto 0); + signal dmem_be : unsigned(3 downto 0); COMPONENT bui @@ -111,8 +111,8 @@ architecture rtl of mips_top is cpu_dmem_err : out STD_LOGIC; cpu_dmem_rdy : out STD_LOGIC; cpu_dmem_en : in STD_LOGIC; - cpu_dmem_re : in STD_LOGIC; - cpu_dmem_we : in unsigned(3 downto 0); + cpu_dmem_we : in STD_LOGIC; + cpu_dmem_be : in unsigned(3 downto 0); cpu_dmem_dout : in word_t; cpu_dmem_din : out word_t; cpu_dmem_addr : in word_t @@ -140,8 +140,8 @@ inst_pipeline: pipeline dmem_err => dmem_err, dmem_rdy => dmem_rdy, dmem_en => dmem_en, - dmem_re => dmem_re, dmem_we => dmem_we, + dmem_be => dmem_be, dmem_addr => dmem_addr, dmem_din => dmem_din, dmem_dout => dmem_dout @@ -170,8 +170,8 @@ inst_bui: bui cpu_dmem_err => dmem_err, cpu_dmem_rdy => dmem_rdy, cpu_dmem_en => dmem_en, - cpu_dmem_re => dmem_re, cpu_dmem_we => dmem_we, + cpu_dmem_be => dmem_be, cpu_dmem_addr => dmem_addr, cpu_dmem_din => dmem_din, cpu_dmem_dout => dmem_dout