diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd
index 3cc809b..6c5b9f1 100644
--- a/lib/CPUs/JCpu/src/core/chipreg.vhd
+++ b/lib/CPUs/JCpu/src/core/chipreg.vhd
@@ -68,17 +68,13 @@ proc_reg_write:
 			reg_cmem_high <= (others => '0');
 			reg_bank_sel <= (others => '0');
 			reg_int_ctrl.enable		<= '0';
-			reg_int_ctrl.polarity	<= '1';
 		elsif rising_edge(clk) then
-			reg_int_ctrl.request <= '0';
 			if we = '1' then
 				case addr is
 				when X"01" =>
 					reg_bank_sel(bank_sel_t'range)	<= din(bank_sel_t'range);
 				when X"03" =>
 					reg_int_ctrl.enable		<= din(0);
-					reg_int_ctrl.polarity	<= din(1);
-					reg_int_ctrl.request	<= din(7);
 				when X"04" =>
 					reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
 				when X"05" =>
@@ -101,7 +97,7 @@ proc_reg_read:
 			when X"02" =>	-- CPU status
 				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
 			when X"03" =>	-- Interrupt control
-				dout <= "000000" & reg_int_ctrl.polarity & reg_int_ctrl.enable;
+				dout <= "0000000" & reg_int_ctrl.enable;
 			when X"04" =>	-- Upper stack bits out
 				dout <= "0000" & reg_cmem_high;
 			when X"05" =>	-- Upper cmem bits out
diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
index 051148a..e28d103 100644
--- a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
+++ b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
@@ -132,8 +132,6 @@ package cpu_pkg is
 	
 	type int_ctrl_in_t is record
 		enable			: std_logic;
-		polarity		: std_logic;
-		request			: std_logic;
 	end record;
 	
 	type creg_ctrl_out_t is record
diff --git a/lib/CPUs/JCpu/src/core/int_ctrl.vhd b/lib/CPUs/JCpu/src/core/int_ctrl.vhd
index f35eb5a..ebff3db 100644
--- a/lib/CPUs/JCpu/src/core/int_ctrl.vhd
+++ b/lib/CPUs/JCpu/src/core/int_ctrl.vhd
@@ -120,7 +120,7 @@ pin_sample:
 		if rising_edge(clk) then
 			int_request <= '0';
 			if ctrl_in.enable = '1' then
-				int_request <= (int_in xor (not ctrl_in.polarity)) or ctrl_in.request;
+				int_request <= int_in;
 			end if;	
 		end if;
 	end process;