diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
index f180b19..e34411b 100644
--- a/lib/filter/src/fir_stage_sys.vhd
+++ b/lib/filter/src/fir_stage_sys.vhd
@@ -124,7 +124,7 @@ begin
 ------------------------------------------------------------
 	proc_pipe_reg: process(clk, xin, hin, mult_pipe(0))
 	begin
-		mult_pipe(0)	<= resize(xin * hin, mult_pipe(0));
+		mult_pipe(0)	<= resize(xin * hin, mult_pipe(0), fixed_wrap, fixed_truncate);
 		if rising_edge(clk) then
 			if ce = '1' then
 				for i in 1 to mult_latency loop