From 5427d4cae0fd99208f7275de4b956b9c261b6d8e Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 25 May 2015 07:25:49 +0000 Subject: [PATCH] - removed constants from sdram_types.vhd and put them to sdram_const.vhd - define burst length in sdram_config git-svn-id: http://moon:8086/svn/vhdl/trunk@1223 cc03376c-175c-47c8-b038-4cd826a8556b --- .../ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo | 1 + .../ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo | 1 + .../ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd | 1 + lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd | 1 + .../src/sdram_config_mt46v16m16.vhd | 16 +---- .../src/sdram_config_mt48lc16m16.vhd | 15 +--- lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd | 68 +++++++++++++++++++ lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd | 7 +- .../src/sdram_ctrl_frontend_wb32.vhd | 1 + .../src/sdram_ctrl_frontend_wb64.vhd | 1 + lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd | 1 + lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd | 19 +----- 12 files changed, 85 insertions(+), 47 deletions(-) create mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo index cc854d7..c104cbb 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo @@ -11,6 +11,7 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" vcom -explicit -93 "../../../misc/utils_pkg.vhd" +vcom -explicit -93 "../src/sdram_const.vhd" vcom -explicit -93 "../src/sdram_config_mt46v16m16.vhd" vcom -explicit -93 "../src/sdram_types.vhd" vcom -explicit -93 "../src/sdram_cmd.vhd" diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo index 6ef1b75..952363a 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo @@ -11,6 +11,7 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" vcom -explicit -93 "../../../misc/utils_pkg.vhd" +vcom -explicit -93 "../src/sdram_const.vhd" vcom -explicit -93 "../src/sdram_config_mt46v16m16.vhd" vcom -explicit -93 "../src/sdram_types.vhd" vcom -explicit -93 "../src/sdram_cmd.vhd" diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd index d686bb3..90fc2d9 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd @@ -25,6 +25,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; +use work.sdram_const.all; use work.sdram_config.all; use work.sdram_types.all; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index 63ee6ad..8d0b00a 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -25,6 +25,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; +use work.sdram_const.all; use work.sdram_config.all; use work.sdram_types.all; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt46v16m16.vhd index 594f244..e84275d 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt46v16m16.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt46v16m16.vhd @@ -25,6 +25,8 @@ library IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +use work.sdram_const.all; + package sdram_config is constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width @@ -38,24 +40,12 @@ package sdram_config is constant BUS_DATA_WIDTH : positive := 2*PART_DATA_WIDTH; -- DDR => twice part data width constant BUS_DM_WIDTH : positive := 2*PART_DM_WIDTH; -- DDR => twice part data width - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - -- DDR SDRAM Hardware defined constants constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; + constant LM_BL_CURR : natural := LMR_BL2; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd index 77dac52..a6638e4 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd @@ -25,6 +25,8 @@ library IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +use work.sdram_const.all; + package sdram_config is constant PART_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width @@ -38,24 +40,13 @@ package sdram_config is constant BUS_DATA_WIDTH : positive := PART_DATA_WIDTH; -- SDR => part data width constant BUS_DM_WIDTH : positive := PART_DM_WIDTH; -- SDR => part data width - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; -- DDR SDRAM Hardware defined constants constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; + constant LM_BL_CURR : natural := LMR_BL1; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd new file mode 100644 index 0000000..8c68698 --- /dev/null +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------- +-- Project: SDRAM controller +-- This file: Type definitions +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.MATH_REAL.ALL; + +package sdram_const is + + ----------------------------------------------------------------------------------------- + -- Table of Timing Parameters as a function of operation + + -- Derived constants from sdram_config + + subtype user_cmd_t is unsigned(1 downto 0); + constant UCMD_NOP : user_cmd_t := "00"; + constant UCMD_READ : user_cmd_t := "01"; + constant UCMD_WRITE : user_cmd_t := "10"; + constant UCMD_LMR : user_cmd_t := "11"; + + subtype sdr_cmd_t is natural range 0 to 9; + constant SD_DESELECT : sdr_cmd_t := 0; + constant SD_NOP : sdr_cmd_t := 1; + constant SD_LMR : sdr_cmd_t := 2; + constant SD_ACT : sdr_cmd_t := 3; + constant SD_READ : sdr_cmd_t := 4; + constant SD_WRITE : sdr_cmd_t := 5; + constant SD_PRE : sdr_cmd_t := 6; + constant SD_BST : sdr_cmd_t := 7; + constant SD_AR : sdr_cmd_t := 8; + constant SD_SR : sdr_cmd_t := 9; + + constant LMR_REG_BASE : natural := 0; + constant LMR_REG_EXTENDED : natural := 1; + constant LMR_OP_NORMAL : natural := 0; + constant LMR_OP_RES_DLL : natural := 2; + constant LMR_BT_SEQ : natural := 0; + constant LMR_BT_ILVD : natural := 1; + constant LMR_BL1 : natural := 0; + constant LMR_BL2 : natural := 1; + constant LMR_BL4 : natural := 2; + constant LMR_BL8 : natural := 3; + constant LMR_CL2 : natural := 2; + constant LMR_CL3 : natural := 3; + constant LMR_CL2_5 : natural := 6; + +end sdram_const; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd index 944d0ab..46ade00 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd @@ -25,6 +25,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; +use work.sdram_const.all; use work.sdram_config.all; use work.sdram_types.all; use work.utils_pkg.all; @@ -55,8 +56,6 @@ end sdram_ctrl; architecture behaviour of sdram_ctrl is - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BURST_LEN); - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH); signal st_ctrl, st_ctrl_next : ctrl_state_t; @@ -129,7 +128,7 @@ architecture behaviour of sdram_ctrl is ), ( cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), + mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LM_BL_CURR, 3), wait_cycle => 200 ), ( @@ -169,7 +168,7 @@ architecture behaviour of sdram_ctrl is ), ( cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), + mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LM_BL_CURR, 3), wait_cycle => 200 ), ( diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd index 75d91d2..8efd396 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd @@ -26,6 +26,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use work.fifo_ctrl_pkg.all; +use work.sdram_const.all; use work.sdram_config.all; use work.sdram_types.all; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd index 80d8f00..0859e11 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd @@ -26,6 +26,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use work.fifo_ctrl_pkg.all; +use work.sdram_const.all; use work.sdram_config.all; use work.sdram_types.all; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index 78dc1a1..03b3b27 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -25,6 +25,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; +use work.sdram_const.all; use work.sdram_config.all; use work.sdram_types.all; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd index 1473f98..d97b304 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd @@ -26,6 +26,7 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.MATH_REAL.ALL; +use work.sdram_const.all; use work.sdram_config.all; package sdram_types is @@ -35,24 +36,6 @@ package sdram_types is -- Derived constants from sdram_config - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); subtype user_addr_t is unsigned(PART_BANK_WIDTH+PART_ROW_ADDR_WIDTH+PART_COL_ADDR_WIDTH-1 downto 0); subtype sdr_addr_t is unsigned(PART_ADDR_WIDTH-1 downto 0);