- read streaming with FIFO full wait

git-svn-id: http://moon:8086/svn/vhdl/trunk@1288 cc03376c-175c-47c8-b038-4cd826a8556b

lib/spi/src/tb_spi_master.vhd

@@ -46,7 +46,7 @@ ARCHITECTURE behavior OF tb_spi_master IS
 	signal mst_din			: unsigned(31 downto 0) := (others => '0');
 	signal mst_dout			: unsigned(31 downto 0);
 	signal mst_dout_vld		: STD_LOGIC;
-	signal mst_dout_re		: STD_LOGIC := '1';
+	signal mst_dout_re		: STD_LOGIC := '0';
 	signal mst_shift_en		: STD_LOGIC := '1';
 	signal mosi				: STD_LOGIC;
 	signal miso				: STD_LOGIC := '0';
@@ -103,6 +103,15 @@ CLK_GEN: process
 		CLK <= not CLK;
 	end process;
 
+mst_dout_re_GEN: process
+	begin
+		wait for 10 us;
+		mst_dout_re <= '1';
+		wait for CLK_PERIOD;
+		mst_dout_re <= '1';
+	end process;
+
+
 RX_SLAVE_SIM_SHIFT_REG: process(mst_clk)
 	begin
 		if rising_edge(mst_clk) then