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git-svn-id: http://moon:8086/svn/vhdl/trunk@1049 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2014-07-23 20:10:34 +00:00
parent 4430b4eb37
commit 52acc7bd34
12 changed files with 3628 additions and 3628 deletions
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lib/radio/cordic/src/cordic_pipe_post.vhd
+107 -107
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@@ -1,107 +1,107 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:16:14 10/02/05 -- Create Date: 12:16:14 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_stage_pre - Behavioral -- Module Name: cordic_stage_pre - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_pipe_post is entity cordic_pipe_post is
Generic Generic
( (
cordic_mode : cordic_mode_t := cordic_mode_rotate; cordic_mode : cordic_mode_t := cordic_mode_rotate;
nstages : integer := 0; nstages : integer := 0;
nbits_x : integer := 8; nbits_x : integer := 8;
nbits_x_frac : integer := 6; nbits_x_frac : integer := 6;
nbits_y : integer := 8; nbits_y : integer := 8;
nbits_y_frac : integer := 6; nbits_y_frac : integer := 6;
nbits_z : integer := 8; nbits_z : integer := 8;
nbits_z_frac : integer := 8 nbits_z_frac : integer := 8
); );
Port Port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
vld_out : out std_logic vld_out : out std_logic
); );
end cordic_pipe_post; end cordic_pipe_post;
architecture Behavioral of cordic_pipe_post is architecture Behavioral of cordic_pipe_post is
constant gain_x : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_x, nbits_x_frac), fixed_wrap, fixed_round); constant gain_x : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_x, nbits_x_frac), fixed_wrap, fixed_round);
constant gain_y : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_y, nbits_y_frac), fixed_wrap, fixed_round); constant gain_y : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_y, nbits_y_frac), fixed_wrap, fixed_round);
------------------------------------------------------------ ------------------------------------------------------------
begin begin
------------------------------------------------------------ ------------------------------------------------------------
cordic_proc_pre_stage: cordic_proc_pre_stage:
process(clk) process(clk)
variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac)); variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac)); variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac)); variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
begin begin
if rising_edge(clk) then if rising_edge(clk) then
vld_out <= '0'; vld_out <= '0';
if rst = '1' then if rst = '1' then
xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0'); xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0'); yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0'); zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
elsif vld_in = '1' then elsif vld_in = '1' then
vld_out <= '1'; vld_out <= '1';
xi := resize(xin, xi); xi := resize(xin, xi);
yi := resize(yin, yi); yi := resize(yin, yi);
zi := resize(zin, zi); zi := resize(zin, zi);
xo := resize(xi * gain_x, xo, cordic_saturate_mode, cordic_round_mode); xo := resize(xi * gain_x, xo, cordic_saturate_mode, cordic_round_mode);
yo := resize(yi * gain_y, yo, cordic_saturate_mode, cordic_round_mode); yo := resize(yi * gain_y, yo, cordic_saturate_mode, cordic_round_mode);
zo := zi; zo := zi;
xout <= xo after tpd; xout <= xo after tpd;
yout <= yo after tpd; yout <= yo after tpd;
zout <= zo after tpd; zout <= zo after tpd;
end if; end if;
end if; end if;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/cordic_pipe_pre.vhd
+137 -137
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@@ -1,137 +1,137 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:16:14 10/02/05 -- Create Date: 12:16:14 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_stage_pre - Behavioral -- Module Name: cordic_stage_pre - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_pipe_pre is entity cordic_pipe_pre is
Generic Generic
( (
cordic_mode : cordic_mode_t := cordic_mode_rotate; cordic_mode : cordic_mode_t := cordic_mode_rotate;
z_range : real := pi; z_range : real := pi;
nbits_x : integer := 8; nbits_x : integer := 8;
nbits_x_frac : integer := 6; nbits_x_frac : integer := 6;
nbits_y : integer := 8; nbits_y : integer := 8;
nbits_y_frac : integer := 6; nbits_y_frac : integer := 6;
nbits_z : integer := 8; nbits_z : integer := 8;
nbits_z_frac : integer := 8 nbits_z_frac : integer := 8
); );
Port Port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
vld_out : out std_logic vld_out : out std_logic
); );
end cordic_pipe_pre; end cordic_pipe_pre;
architecture Behavioral of cordic_pipe_pre is architecture Behavioral of cordic_pipe_pre is
constant pi_sfix : sfixed := to_sfixed(z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round); constant pi_sfix : sfixed := to_sfixed(z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
constant pi2_sfix : sfixed := to_sfixed(z_range/2.0, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round); constant pi2_sfix : sfixed := to_sfixed(z_range/2.0, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
------------------------------------------------------------ ------------------------------------------------------------
begin begin
------------------------------------------------------------ ------------------------------------------------------------
cordic_proc_pre_stage: cordic_proc_pre_stage:
process(clk) process(clk)
variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac)); variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac)); variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac)); variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
begin begin
if rising_edge(clk) then if rising_edge(clk) then
vld_out <= '0'; vld_out <= '0';
if rst = '1' then if rst = '1' then
xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0'); xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0'); yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0'); zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
elsif vld_in = '1' then elsif vld_in = '1' then
vld_out <= '1'; vld_out <= '1';
xi := xin; xi := xin;
yi := yin; yi := yin;
zi := zin; zi := zin;
xo := xi; xo := xi;
yo := yi; yo := yi;
zo := zi; zo := zi;
if (zi < -pi2_sfix) then if (zi < -pi2_sfix) then
xo := resize(-xi, xo); xo := resize(-xi, xo);
yo := resize(-yi, yo); yo := resize(-yi, yo);
zo := resize(zi + pi_sfix, zo); zo := resize(zi + pi_sfix, zo);
elsif (zi > pi2_sfix) then elsif (zi > pi2_sfix) then
xo := resize(-xi, xo); xo := resize(-xi, xo);
yo := resize(-yi, yo); yo := resize(-yi, yo);
zo := resize(zi - pi_sfix, zo); zo := resize(zi - pi_sfix, zo);
end if; end if;
xout <= xo after tpd; xout <= xo after tpd;
yout <= yo after tpd; yout <= yo after tpd;
zout <= zo after tpd; zout <= zo after tpd;
end if; end if;
end if; end if;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
end Behavioral; end Behavioral;
-- if (y < 0) then -- if (y < 0) then
-- x' = -y -- x' = -y
-- y' = x -- y' = x
-- z' = z + pi/2; -- z' = z + pi/2;
-- else -- else
-- x' = y -- x' = y
-- y' = -x -- y' = -x
-- z' = z - pi/2; -- z' = z - pi/2;
-- end if; -- end if;
-- --
-- if (x < 0) then -- if (x < 0) then
-- x' = -x; -- x' = -x;
-- y' = -y; -- y' = -y;
-- z' = z - pi -- z' = z - pi
-- else -- else
-- x' = x; -- x' = x;
-- y' = y; -- y' = y;
-- z' = z -- z' = z
-- end if; -- end if;
lib/radio/cordic/src/cordic_pipe_stage.vhd
+115 -115
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@@ -1,115 +1,115 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:16:14 10/02/05 -- Create Date: 12:16:14 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_stage - Behavioral -- Module Name: cordic_stage - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_pipe_stage is entity cordic_pipe_stage is
Generic Generic
( (
cordic_mode : cordic_mode_t := cordic_mode_rotate; cordic_mode : cordic_mode_t := cordic_mode_rotate;
z_range : real := pi; z_range : real := pi;
stage_num : integer := 0; stage_num : integer := 0;
nbits_x : integer := 8; nbits_x : integer := 8;
nbits_x_frac : integer := 6; nbits_x_frac : integer := 6;
nbits_y : integer := 8; nbits_y : integer := 8;
nbits_y_frac : integer := 6; nbits_y_frac : integer := 6;
nbits_z : integer := 8; nbits_z : integer := 8;
nbits_z_frac : integer := 8 nbits_z_frac : integer := 8
); );
Port Port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
vld_out : out std_logic vld_out : out std_logic
); );
end cordic_pipe_stage; end cordic_pipe_stage;
architecture Behavioral of cordic_pipe_stage is architecture Behavioral of cordic_pipe_stage is
constant coeff : sfixed := to_sfixed(arctan_tbl(stage_num)*z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round); constant coeff : sfixed := to_sfixed(arctan_tbl(stage_num)*z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
begin begin
------------------------------------------------------------ ------------------------------------------------------------
cordic_proc_stage: cordic_proc_stage:
process(clk) process(clk)
variable xi, xt, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac)); variable xi, xt, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
variable yi, yt, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac)); variable yi, yt, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac)); variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
begin begin
if rising_edge(clk) then if rising_edge(clk) then
vld_out <= '0'; vld_out <= '0';
if rst = '1' then if rst = '1' then
xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0'); xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0'); yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0'); zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
elsif vld_in = '1' then elsif vld_in = '1' then
vld_out <= '1'; vld_out <= '1';
xi := xin; xi := xin;
yi := yin; yi := yin;
zi := zin; zi := zin;
xt := xi sra stage_num; xt := xi sra stage_num;
yt := yi sra stage_num; yt := yi sra stage_num;
if zi(zi'high) = '1' then if zi(zi'high) = '1' then
xo := resize(xi + yt, xo); xo := resize(xi + yt, xo);
yo := resize(yi - xt, yo); yo := resize(yi - xt, yo);
zo := resize(zi + coeff, zo); zo := resize(zi + coeff, zo);
else else
xo := resize(xi - yt, xo); xo := resize(xi - yt, xo);
yo := resize(yi + xt, yo); yo := resize(yi + xt, yo);
zo := resize(zi - coeff, zo); zo := resize(zi - coeff, zo);
end if; end if;
xout <= xo after tpd; xout <= xo after tpd;
yout <= yo after tpd; yout <= yo after tpd;
zout <= zo after tpd; zout <= zo after tpd;
end if; end if;
end if; end if;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/cordic_pipe_top.vhd
+319 -319
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@@ -1,319 +1,319 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 11:52:30 10/02/05 -- Create Date: 11:52:30 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_top - Behavioral -- Module Name: cordic_top - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL; use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_pipe_top is entity cordic_pipe_top is
Generic Generic
( (
cordic_mode : cordic_mode_t := cordic_mode_rotate; cordic_mode : cordic_mode_t := cordic_mode_rotate;
z_range : real := 1.0; z_range : real := 1.0;
gain_corr_mode : gain_corr_mode_t := gain_mode_disabled; gain_corr_mode : gain_corr_mode_t := gain_mode_disabled;
nstages : integer := 18; nstages : integer := 18;
nbits_x_in : integer := 18; nbits_x_in : integer := 18;
nbits_y_in : integer := 18; nbits_y_in : integer := 18;
nbits_z_in : integer := 18; nbits_z_in : integer := 18;
nbits_frac_x_in : integer := 16; nbits_frac_x_in : integer := 16;
nbits_frac_y_in : integer := 16; nbits_frac_y_in : integer := 16;
nbits_frac_z_in : integer := 16; nbits_frac_z_in : integer := 16;
nbits_x_out : integer := 18; nbits_x_out : integer := 18;
nbits_y_out : integer := 18; nbits_y_out : integer := 18;
nbits_z_out : integer := 18; nbits_z_out : integer := 18;
nbits_frac_x_out : integer := 17; nbits_frac_x_out : integer := 17;
nbits_frac_y_out : integer := 17; nbits_frac_y_out : integer := 17;
nbits_frac_z_out : integer := 17 nbits_frac_z_out : integer := 17
); );
Port Port
( (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
xin : in sfixed(shi(nbits_x_in, nbits_frac_x_in) downto slo(nbits_x_in, nbits_frac_x_in)); xin : in sfixed(shi(nbits_x_in, nbits_frac_x_in) downto slo(nbits_x_in, nbits_frac_x_in));
yin : in sfixed(shi(nbits_y_in, nbits_frac_y_in) downto slo(nbits_y_in, nbits_frac_y_in)); yin : in sfixed(shi(nbits_y_in, nbits_frac_y_in) downto slo(nbits_y_in, nbits_frac_y_in));
zin : in sfixed(shi(nbits_z_in, nbits_frac_z_in) downto slo(nbits_z_in, nbits_frac_z_in)); zin : in sfixed(shi(nbits_z_in, nbits_frac_z_in) downto slo(nbits_z_in, nbits_frac_z_in));
xout : out sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); xout : out sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
yout : out sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); yout : out sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
zout : out sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); zout : out sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
vld_out : out std_logic vld_out : out std_logic
); );
end cordic_pipe_top; end cordic_pipe_top;
architecture Behavioral of cordic_pipe_top is architecture Behavioral of cordic_pipe_top is
----------------------------------------------------------------------- -----------------------------------------------------------------------
COMPONENT cordic_pipe_pre is COMPONENT cordic_pipe_pre is
GENERIC GENERIC
( (
cordic_mode : cordic_mode_t; cordic_mode : cordic_mode_t;
z_range : real; z_range : real;
nbits_x : integer; nbits_x : integer;
nbits_x_frac : integer; nbits_x_frac : integer;
nbits_y : integer; nbits_y : integer;
nbits_y_frac : integer; nbits_y_frac : integer;
nbits_z : integer; nbits_z : integer;
nbits_z_frac : integer nbits_z_frac : integer
); );
PORT( PORT(
rst : IN std_logic; rst : IN std_logic;
clk : IN std_logic; clk : IN std_logic;
vld_in : IN std_logic; vld_in : IN std_logic;
xin : IN sfixed; xin : IN sfixed;
yin : IN sfixed; yin : IN sfixed;
zin : IN sfixed; zin : IN sfixed;
xout : OUT sfixed; xout : OUT sfixed;
yout : OUT sfixed; yout : OUT sfixed;
zout : OUT sfixed; zout : OUT sfixed;
vld_out : out std_logic vld_out : out std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT cordic_pipe_stage COMPONENT cordic_pipe_stage
GENERIC GENERIC
( (
cordic_mode : cordic_mode_t; cordic_mode : cordic_mode_t;
z_range : real; z_range : real;
stage_num : integer; stage_num : integer;
nbits_x : integer; nbits_x : integer;
nbits_x_frac : integer; nbits_x_frac : integer;
nbits_y : integer; nbits_y : integer;
nbits_y_frac : integer; nbits_y_frac : integer;
nbits_z : integer; nbits_z : integer;
nbits_z_frac : integer nbits_z_frac : integer
); );
PORT( PORT(
rst : IN std_logic; rst : IN std_logic;
clk : IN std_logic; clk : IN std_logic;
vld_in : IN std_logic; vld_in : IN std_logic;
xin : IN sfixed; xin : IN sfixed;
yin : IN sfixed; yin : IN sfixed;
zin : IN sfixed; zin : IN sfixed;
xout : OUT sfixed; xout : OUT sfixed;
yout : OUT sfixed; yout : OUT sfixed;
zout : OUT sfixed; zout : OUT sfixed;
vld_out : out std_logic vld_out : out std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT cordic_pipe_post is COMPONENT cordic_pipe_post is
GENERIC GENERIC
( (
cordic_mode : cordic_mode_t; cordic_mode : cordic_mode_t;
nstages : integer; nstages : integer;
nbits_x : integer; nbits_x : integer;
nbits_x_frac : integer; nbits_x_frac : integer;
nbits_y : integer; nbits_y : integer;
nbits_y_frac : integer; nbits_y_frac : integer;
nbits_z : integer; nbits_z : integer;
nbits_z_frac : integer nbits_z_frac : integer
); );
PORT( PORT(
rst : IN std_logic; rst : IN std_logic;
clk : IN std_logic; clk : IN std_logic;
vld_in : IN std_logic; vld_in : IN std_logic;
xin : IN sfixed; xin : IN sfixed;
yin : IN sfixed; yin : IN sfixed;
zin : IN sfixed; zin : IN sfixed;
xout : OUT sfixed; xout : OUT sfixed;
yout : OUT sfixed; yout : OUT sfixed;
zout : OUT sfixed; zout : OUT sfixed;
vld_out : out std_logic vld_out : out std_logic
); );
END COMPONENT; END COMPONENT;
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- Define number of internal stage bits -- Define number of internal stage bits
constant stage_x_nbits : integer := nbits_x_in + integer(log2(real(nbits_x_in))+0.5); constant stage_x_nbits : integer := nbits_x_in + integer(log2(real(nbits_x_in))+0.5);
constant stage_x_nbits_frac : integer := nbits_frac_x_in + integer(log2(real(nbits_x_in))+0.5); constant stage_x_nbits_frac : integer := nbits_frac_x_in + integer(log2(real(nbits_x_in))+0.5);
constant stage_y_nbits : integer := nbits_y_in + integer(log2(real(nbits_y_in))+0.5); constant stage_y_nbits : integer := nbits_y_in + integer(log2(real(nbits_y_in))+0.5);
constant stage_y_nbits_frac : integer := nbits_frac_y_in + integer(log2(real(nbits_y_in))+0.5); constant stage_y_nbits_frac : integer := nbits_frac_y_in + integer(log2(real(nbits_y_in))+0.5);
constant stage_z_nbits : integer := nbits_z_in + integer(log2(real(nbits_z_in))+0.5); constant stage_z_nbits : integer := nbits_z_in + integer(log2(real(nbits_z_in))+0.5);
constant stage_z_nbits_frac : integer := nbits_frac_z_in + integer(log2(real(nbits_z_in))+0.5); constant stage_z_nbits_frac : integer := nbits_frac_z_in + integer(log2(real(nbits_z_in))+0.5);
-- INPUT -- INPUT
-- Input pre stage -- Input pre stage
signal pre_xin : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac)); signal pre_xin : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
signal pre_yin : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac)); signal pre_yin : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
signal pre_zin : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac)); signal pre_zin : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
signal pre_xout : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac)); signal pre_xout : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
signal pre_yout : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac)); signal pre_yout : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
signal pre_zout : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac)); signal pre_zout : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-- Input processing stage -- Input processing stage
subtype stage_x_t is sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac)); subtype stage_x_t is sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
subtype stage_y_t is sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac)); subtype stage_y_t is sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
subtype stage_z_t is sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac)); subtype stage_z_t is sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
type stage_x_array_t is array(0 to nstages) of stage_x_t; type stage_x_array_t is array(0 to nstages) of stage_x_t;
type stage_y_array_t is array(0 to nstages) of stage_y_t; type stage_y_array_t is array(0 to nstages) of stage_y_t;
type stage_z_array_t is array(0 to nstages) of stage_z_t; type stage_z_array_t is array(0 to nstages) of stage_z_t;
signal stage_vld: unsigned(0 to nstages); signal stage_vld: unsigned(0 to nstages);
signal stage_x : stage_x_array_t; signal stage_x : stage_x_array_t;
signal stage_y : stage_y_array_t; signal stage_y : stage_y_array_t;
signal stage_z : stage_z_array_t; signal stage_z : stage_z_array_t;
-- Output post stage -- Output post stage
signal post_xin : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); signal post_xin : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
signal post_yin : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); signal post_yin : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
signal post_zin : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); signal post_zin : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
signal post_xout : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); signal post_xout : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
signal post_yout : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); signal post_yout : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
signal post_zout : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); signal post_zout : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
signal post_vld : std_logic; signal post_vld : std_logic;
begin begin
pre_xin <= resize(xin, pre_xin); pre_xin <= resize(xin, pre_xin);
pre_yin <= resize(yin, pre_yin); pre_yin <= resize(yin, pre_yin);
pre_zin <= resize(zin, pre_zin); pre_zin <= resize(zin, pre_zin);
stage_x(0) <= resize(pre_xout, stage_x(0)); stage_x(0) <= resize(pre_xout, stage_x(0));
stage_y(0) <= resize(pre_yout, stage_y(0)); stage_y(0) <= resize(pre_yout, stage_y(0));
stage_z(0) <= resize(pre_zout, stage_z(0)); stage_z(0) <= resize(pre_zout, stage_z(0));
post_xin <= resize(stage_x(nstages), post_xin, cordic_saturate_mode, cordic_round_mode); post_xin <= resize(stage_x(nstages), post_xin, cordic_saturate_mode, cordic_round_mode);
post_yin <= resize(stage_y(nstages), post_yin, cordic_saturate_mode, cordic_round_mode); post_yin <= resize(stage_y(nstages), post_yin, cordic_saturate_mode, cordic_round_mode);
post_zin <= resize(stage_z(nstages), post_zin, cordic_saturate_mode, cordic_round_mode); post_zin <= resize(stage_z(nstages), post_zin, cordic_saturate_mode, cordic_round_mode);
gen_output_unity: gen_output_unity:
if gain_corr_mode = gain_mode_unity generate if gain_corr_mode = gain_mode_unity generate
begin begin
xout <= post_xout; xout <= post_xout;
yout <= post_yout; yout <= post_yout;
zout <= post_zout; zout <= post_zout;
vld_out <= post_vld; vld_out <= post_vld;
end generate; end generate;
gen_output_disabled: gen_output_disabled:
if gain_corr_mode = gain_mode_disabled generate if gain_corr_mode = gain_mode_disabled generate
begin begin
xout <= post_xin; xout <= post_xin;
yout <= post_yin; yout <= post_yin;
zout <= post_zin; zout <= post_zin;
vld_out <= stage_vld(nstages); vld_out <= stage_vld(nstages);
end generate; end generate;
----------------------------------------------------------------------- -----------------------------------------------------------------------
Inst_cordic_pipe_pre: cordic_pipe_pre Inst_cordic_pipe_pre: cordic_pipe_pre
GENERIC MAP GENERIC MAP
( (
cordic_mode => cordic_mode_rotate, cordic_mode => cordic_mode_rotate,
z_range => z_range, z_range => z_range,
nbits_x => stage_x_nbits, nbits_x => stage_x_nbits,
nbits_x_frac => stage_x_nbits_frac, nbits_x_frac => stage_x_nbits_frac,
nbits_y => stage_y_nbits, nbits_y => stage_y_nbits,
nbits_y_frac => stage_y_nbits_frac, nbits_y_frac => stage_y_nbits_frac,
nbits_z => stage_z_nbits, nbits_z => stage_z_nbits,
nbits_z_frac => stage_z_nbits_frac nbits_z_frac => stage_z_nbits_frac
) )
PORT MAP PORT MAP
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
vld_in => vld_in, vld_in => vld_in,
xin => pre_xin, xin => pre_xin,
yin => pre_yin, yin => pre_yin,
zin => pre_zin, zin => pre_zin,
xout => pre_xout, xout => pre_xout,
yout => pre_yout, yout => pre_yout,
zout => pre_zout, zout => pre_zout,
vld_out => stage_vld(0) vld_out => stage_vld(0)
); );
gen_pipe: gen_pipe:
for i in 1 to nstages generate for i in 1 to nstages generate
Inst_cordic_pipe: cordic_pipe_stage Inst_cordic_pipe: cordic_pipe_stage
GENERIC MAP GENERIC MAP
( (
cordic_mode => cordic_mode_rotate, cordic_mode => cordic_mode_rotate,
z_range => z_range, z_range => z_range,
stage_num => i-1, stage_num => i-1,
nbits_x => stage_x_nbits, nbits_x => stage_x_nbits,
nbits_x_frac => stage_x_nbits_frac, nbits_x_frac => stage_x_nbits_frac,
nbits_y => stage_y_nbits, nbits_y => stage_y_nbits,
nbits_y_frac => stage_y_nbits_frac, nbits_y_frac => stage_y_nbits_frac,
nbits_z => stage_z_nbits, nbits_z => stage_z_nbits,
nbits_z_frac => stage_z_nbits_frac nbits_z_frac => stage_z_nbits_frac
) )
PORT MAP PORT MAP
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
vld_in => stage_vld(i-1), vld_in => stage_vld(i-1),
xin => stage_x(i-1), xin => stage_x(i-1),
yin => stage_y(i-1), yin => stage_y(i-1),
zin => stage_z(i-1), zin => stage_z(i-1),
xout => stage_x(i), xout => stage_x(i),
yout => stage_y(i), yout => stage_y(i),
zout => stage_z(i), zout => stage_z(i),
vld_out => stage_vld(i) vld_out => stage_vld(i)
); );
end generate; end generate;
gen_post_process: gen_post_process:
if gain_corr_mode = gain_mode_unity generate if gain_corr_mode = gain_mode_unity generate
begin begin
Inst_cordic_pipe_post: cordic_pipe_post Inst_cordic_pipe_post: cordic_pipe_post
GENERIC MAP GENERIC MAP
( (
cordic_mode => cordic_mode_rotate, cordic_mode => cordic_mode_rotate,
nstages => nstages, nstages => nstages,
nbits_x => nbits_x_out, nbits_x => nbits_x_out,
nbits_x_frac => nbits_frac_x_out, nbits_x_frac => nbits_frac_x_out,
nbits_y => nbits_y_out, nbits_y => nbits_y_out,
nbits_y_frac => nbits_frac_y_out, nbits_y_frac => nbits_frac_y_out,
nbits_z => nbits_z_out, nbits_z => nbits_z_out,
nbits_z_frac => nbits_frac_z_out nbits_z_frac => nbits_frac_z_out
) )
PORT MAP PORT MAP
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
vld_in => stage_vld(nstages), vld_in => stage_vld(nstages),
xin => post_xin, xin => post_xin,
yin => post_yin, yin => post_yin,
zin => post_zin, zin => post_zin,
xout => post_xout, xout => post_xout,
yout => post_yout, yout => post_yout,
zout => post_zout, zout => post_zout,
vld_out => post_vld vld_out => post_vld
); );
end generate; end generate;
-------------------------------------------------------------------- --------------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/cordic_pkg.vhd
+208 -208
View File
@@ -1,208 +1,208 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all; use ieee.numeric_std.all;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
package cordic_pkg is package cordic_pkg is
constant tpd : time := 0 ns; constant tpd : time := 0 ns;
type cordic_mode_t is (none, cordic_mode_rotate, cordic_mode_vector); type cordic_mode_t is (none, cordic_mode_rotate, cordic_mode_vector);
type reg_mode_t is (none, reg_mode_in, reg_mode_out, reg_mode_inout); type reg_mode_t is (none, reg_mode_in, reg_mode_out, reg_mode_inout);
type gain_corr_mode_t is (gain_mode_disabled, gain_mode_unity); type gain_corr_mode_t is (gain_mode_disabled, gain_mode_unity);
-- Global set arithmetic rounding mode -- Global set arithmetic rounding mode
constant cordic_round_mode : fixed_round_style_type := fixed_round; constant cordic_round_mode : fixed_round_style_type := fixed_round;
-- Global set arithmetic saturating mode -- Global set arithmetic saturating mode
constant cordic_saturate_mode : fixed_overflow_style_type := fixed_wrap; constant cordic_saturate_mode : fixed_overflow_style_type := fixed_wrap;
constant max_iteration : integer := 80; constant max_iteration : integer := 80;
-- Normalized Arctan table (for phases z = -1..+1) -- Normalized Arctan table (for phases z = -1..+1)
-- MatLab command: arctan_tbl = (atan(2.^-(0:N-1))/pi)' -- MatLab command: arctan_tbl = (atan(2.^-(0:N-1))/pi)'
-- (Print format: long e, compact) -- (Print format: long e, compact)
constant arctan_tbl : real_array_t (0 to max_iteration-1) := constant arctan_tbl : real_array_t (0 to max_iteration-1) :=
( (
2.500000000000000e-001, 2.500000000000000e-001,
1.475836176504333e-001, 1.475836176504333e-001,
7.797913037736932e-002, 7.797913037736932e-002,
3.958342416056555e-002, 3.958342416056555e-002,
1.986852430554084e-002, 1.986852430554084e-002,
9.943947823589275e-003, 9.943947823589275e-003,
4.973187278950414e-003, 4.973187278950414e-003,
2.486745393669739e-003, 2.486745393669739e-003,
1.243391668714101e-003, 1.243391668714101e-003,
6.216982059233716e-004, 6.216982059233716e-004,
3.108493994100204e-004, 3.108493994100204e-004,
1.554247367611316e-004, 1.554247367611316e-004,
7.771237301258342e-005, 7.771237301258342e-005,
3.885618708529400e-005, 3.885618708529400e-005,
1.942809361502228e-005, 1.942809361502228e-005,
9.714046816558053e-006, 9.714046816558053e-006,
4.857023409409890e-006, 4.857023409409890e-006,
2.428511704846303e-006, 2.428511704846303e-006,
1.214255852440821e-006, 1.214255852440821e-006,
6.071279262226194e-007, 6.071279262226194e-007,
3.035639631115858e-007, 3.035639631115858e-007,
1.517819815558274e-007, 1.517819815558274e-007,
7.589099077791802e-008, 7.589099077791802e-008,
3.794549538895954e-008, 3.794549538895954e-008,
1.897274769447984e-008, 1.897274769447984e-008,
9.486373847239929e-009, 9.486373847239929e-009,
4.743186923619965e-009, 4.743186923619965e-009,
2.371593461809983e-009, 2.371593461809983e-009,
1.185796730904992e-009, 1.185796730904992e-009,
5.928983654524958e-010, 5.928983654524958e-010,
2.964491827262479e-010, 2.964491827262479e-010,
1.482245913631239e-010, 1.482245913631239e-010,
7.411229568156197e-011, 7.411229568156197e-011,
3.705614784078099e-011, 3.705614784078099e-011,
1.852807392039049e-011, 1.852807392039049e-011,
9.264036960195246e-012, 9.264036960195246e-012,
4.632018480097623e-012, 4.632018480097623e-012,
2.316009240048812e-012, 2.316009240048812e-012,
1.158004620024406e-012, 1.158004620024406e-012,
5.790023100122029e-013, 5.790023100122029e-013,
2.895011550061015e-013, 2.895011550061015e-013,
1.447505775030507e-013, 1.447505775030507e-013,
7.237528875152536e-014, 7.237528875152536e-014,
3.618764437576268e-014, 3.618764437576268e-014,
1.809382218788134e-014, 1.809382218788134e-014,
9.046911093940670e-015, 9.046911093940670e-015,
4.523455546970335e-015, 4.523455546970335e-015,
2.261727773485168e-015, 2.261727773485168e-015,
1.130863886742584e-015, 1.130863886742584e-015,
5.654319433712919e-016, 5.654319433712919e-016,
2.827159716856459e-016, 2.827159716856459e-016,
1.413579858428230e-016, 1.413579858428230e-016,
7.067899292141149e-017, 7.067899292141149e-017,
3.533949646070574e-017, 3.533949646070574e-017,
1.766974823035287e-017, 1.766974823035287e-017,
8.834874115176436e-018, 8.834874115176436e-018,
4.417437057588218e-018, 4.417437057588218e-018,
2.208718528794109e-018, 2.208718528794109e-018,
1.104359264397055e-018, 1.104359264397055e-018,
5.521796321985272e-019, 5.521796321985272e-019,
2.760898160992636e-019, 2.760898160992636e-019,
1.380449080496318e-019, 1.380449080496318e-019,
6.902245402481590e-020, 6.902245402481590e-020,
3.451122701240795e-020, 3.451122701240795e-020,
1.725561350620398e-020, 1.725561350620398e-020,
8.627806753101988e-021, 8.627806753101988e-021,
4.313903376550994e-021, 4.313903376550994e-021,
2.156951688275497e-021, 2.156951688275497e-021,
1.078475844137749e-021, 1.078475844137749e-021,
5.392379220688743e-022, 5.392379220688743e-022,
2.696189610344371e-022, 2.696189610344371e-022,
1.348094805172186e-022, 1.348094805172186e-022,
6.740474025860928e-023, 6.740474025860928e-023,
3.370237012930464e-023, 3.370237012930464e-023,
1.685118506465232e-023, 1.685118506465232e-023,
8.425592532326160e-024, 8.425592532326160e-024,
4.212796266163080e-024, 4.212796266163080e-024,
2.106398133081540e-024, 2.106398133081540e-024,
1.053199066540770e-024, 1.053199066540770e-024,
5.265995332703850e-025 5.265995332703850e-025
); );
-- Gain correction table -- Gain correction table
-- MatLab command: gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))' -- MatLab command: gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
-- (Print format: long e, compact) -- (Print format: long e, compact)
constant gain_tbl : real_array_t (0 to max_iteration-1) := constant gain_tbl : real_array_t (0 to max_iteration-1) :=
( (
7.071067811865475e-001, 7.071067811865475e-001,
6.324555320336759e-001, 6.324555320336759e-001,
6.135719910778963e-001, 6.135719910778963e-001,
6.088339125177524e-001, 6.088339125177524e-001,
6.076482562561681e-001, 6.076482562561681e-001,
6.073517701412959e-001, 6.073517701412959e-001,
6.072776440935260e-001, 6.072776440935260e-001,
6.072591122988928e-001, 6.072591122988928e-001,
6.072544793325624e-001, 6.072544793325624e-001,
6.072533210898752e-001, 6.072533210898752e-001,
6.072530315291344e-001, 6.072530315291344e-001,
6.072529591389448e-001, 6.072529591389448e-001,
6.072529410413973e-001, 6.072529410413973e-001,
6.072529365170103e-001, 6.072529365170103e-001,
6.072529353859135e-001, 6.072529353859135e-001,
6.072529351031394e-001, 6.072529351031394e-001,
6.072529350324457e-001, 6.072529350324457e-001,
6.072529350147724e-001, 6.072529350147724e-001,
6.072529350103540e-001, 6.072529350103540e-001,
6.072529350092495e-001, 6.072529350092495e-001,
6.072529350089733e-001, 6.072529350089733e-001,
6.072529350089043e-001, 6.072529350089043e-001,
6.072529350088870e-001, 6.072529350088870e-001,
6.072529350088827e-001, 6.072529350088827e-001,
6.072529350088816e-001, 6.072529350088816e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001, 6.072529350088813e-001,
6.072529350088813e-001 6.072529350088813e-001
); );
end; -- package cordic_pkg; end; -- package cordic_pkg;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
package body cordic_pkg is package body cordic_pkg is
end; -- package body cordic_pkg; end; -- package body cordic_pkg;
lib/radio/cordic/src/cordic_rom.vhd
+84 -84
View File
@@ -1,84 +1,84 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:37:26 10/02/05 -- Create Date: 12:37:26 10/02/05
-- Design Name: -- Design Name:
-- Module Name: coeff_rom - Behavioral -- Module Name: coeff_rom - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity rom_arctan is entity rom_arctan is
Generic Generic
( (
nbits : integer := 8; nbits : integer := 8;
nbits_frac : integer := 8 nbits_frac : integer := 8
); );
Port Port
( (
addr : in unsigned(6 downto 0); addr : in unsigned(6 downto 0);
dout : out sfixed dout : out sfixed
); );
end rom_arctan; end rom_arctan;
architecture Behavioral of rom_arctan is architecture Behavioral of rom_arctan is
subtype word_t is sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); subtype word_t is sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
type rom_t is array (natural range <>) of word_t; type rom_t is array (natural range <>) of word_t;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
function rom_gen(nstages : integer; round_mode : fixed_round_style_type) return rom_t is function rom_gen(nstages : integer; round_mode : fixed_round_style_type) return rom_t is
variable rom : rom_t (0 to nstages-1); variable rom : rom_t (0 to nstages-1);
variable word : word_t; variable word : word_t;
begin begin
for i in 0 to nstages-1 loop for i in 0 to nstages-1 loop
word := to_sfixed(arctan_tbl(i)*pi, word, fixed_wrap, round_mode); word := to_sfixed(arctan_tbl(i)*pi, word, fixed_wrap, round_mode);
rom(i) := word; rom(i) := word;
end loop; end loop;
return rom; return rom;
end rom_gen; end rom_gen;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Create ROM -- Create ROM
constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode); constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
begin begin
-- ROM implementation -- ROM implementation
rom_arctan: process(addr) rom_arctan: process(addr)
begin begin
dout <= arctan_rom(to_integer(addr)); dout <= arctan_rom(to_integer(addr));
end process; end process;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/cordic_stage.vhd
+291 -291
View File
@@ -1,291 +1,291 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:16:14 10/02/05 -- Create Date: 12:16:14 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_stage - Behavioral -- Module Name: cordic_stage - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_stage is entity cordic_stage is
Generic Generic
( (
nbits : integer := 8; nbits : integer := 8;
nbits_frac : integer := 6; nbits_frac : integer := 6;
nbits_out : integer := 8; nbits_out : integer := 8;
nbits_frac_out : integer := 6; nbits_frac_out : integer := 6;
reg_mode : reg_mode_t := reg_mode_in reg_mode : reg_mode_t := reg_mode_in
); );
Port Port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
ce : in std_logic; ce : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
coeff : in sfixed; coeff : in sfixed;
dir_cw : in std_logic; dir_cw : in std_logic;
stage_count : in integer; stage_count : in integer;
cordic_mode : in cordic_mode_t; cordic_mode : in cordic_mode_t;
ready : out std_logic; ready : out std_logic;
valid : out std_logic valid : out std_logic
); );
end cordic_stage; end cordic_stage;
architecture Behavioral of cordic_stage is architecture Behavioral of cordic_stage is
type xyz_in_t is record type xyz_in_t is record
x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
end record; end record;
type xyz_out_t is record type xyz_out_t is record
x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
end record; end record;
constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
signal xyz_in : xyz_in_t; signal xyz_in : xyz_in_t;
signal xyz_out : xyz_out_t; signal xyz_out : xyz_out_t;
signal valid_r, ready_r : std_logic; signal valid_r, ready_r : std_logic;
begin begin
------------------------------------------------------------ ------------------------------------------------------------
gen_direct: if reg_mode = none generate gen_direct: if reg_mode = none generate
reg_in : process (rst, ce, xin, yin, zin) reg_in : process (rst, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
else else
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end process; end process;
reg_out : process (rst, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
else else
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_in: if (reg_mode = reg_mode_in) generate gen_reg_in: if (reg_mode = reg_mode_in) generate
reg_in : process (rst, clk, ce, xin, yin, zin) reg_in : process (rst, clk, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
if (ce = '1') then if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end if; end if;
end process; end process;
reg_out : process (rst, ready_r, valid_r, xyz_out) reg_out : process (rst, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
else else
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_out: if (reg_mode = reg_mode_out) generate gen_reg_out: if (reg_mode = reg_mode_out) generate
reg_in : process (rst, ce, xin, yin, zin) reg_in : process (rst, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
else else
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end process; end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
if (ce = '1') then if (ce = '1') then
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_inout: if (reg_mode = reg_mode_inout) generate gen_reg_inout: if (reg_mode = reg_mode_inout) generate
reg_in : process (rst, clk, ce, xin, yin, zin) reg_in : process (rst, clk, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
if (ce = '1') then if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end if; end if;
end process; end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
if (ce = '1') then if (ce = '1') then
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
cordic_proc_stage: process(rst, clk, ce, stage_count, coeff, dir_cw, xyz_in) cordic_proc_stage: process(rst, clk, ce, stage_count, coeff, dir_cw, xyz_in)
variable dir_cw_r : std_logic; variable dir_cw_r : std_logic;
variable stage_count_r : integer range 0 to nbits-1; variable stage_count_r : integer range 0 to nbits-1;
variable x2, y2 : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); variable x2, y2 : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
begin begin
if (rst = '1') then if (rst = '1') then
dir_cw_r := dir_cw; dir_cw_r := dir_cw;
stage_count_r := 0; stage_count_r := 0;
x2 := zero_in_sfix; x2 := zero_in_sfix;
y2 := zero_in_sfix; y2 := zero_in_sfix;
xyz_out.x <= zero_out_sfix; xyz_out.x <= zero_out_sfix;
xyz_out.y <= zero_out_sfix; xyz_out.y <= zero_out_sfix;
xyz_out.z <= zero_out_sfix; xyz_out.z <= zero_out_sfix;
else else
if (clk'event and clk = '1') then if (clk'event and clk = '1') then
dir_cw_r := dir_cw; dir_cw_r := dir_cw;
stage_count_r := stage_count; stage_count_r := stage_count;
end if; end if;
x2 := xyz_in.x sra stage_count_r; x2 := xyz_in.x sra stage_count_r;
y2 := xyz_in.y sra stage_count_r; y2 := xyz_in.y sra stage_count_r;
if (dir_cw_r = '1') then if (dir_cw_r = '1') then
xyz_out.x <= resize(xyz_in.x + y2, xyz_out.x'left, xyz_out.x'right) after tpd; xyz_out.x <= resize(xyz_in.x + y2, xyz_out.x'left, xyz_out.x'right) after tpd;
xyz_out.y <= resize(xyz_in.y - x2, xyz_out.y'left, xyz_out.y'right) after tpd; xyz_out.y <= resize(xyz_in.y - x2, xyz_out.y'left, xyz_out.y'right) after tpd;
xyz_out.z <= resize(xyz_in.z + coeff, xyz_out.z'left, xyz_out.z'right) after tpd; xyz_out.z <= resize(xyz_in.z + coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
else else
xyz_out.x <= resize(xyz_in.x - y2, xyz_out.x'left, xyz_out.x'right) after tpd; xyz_out.x <= resize(xyz_in.x - y2, xyz_out.x'left, xyz_out.x'right) after tpd;
xyz_out.y <= resize(xyz_in.y + x2, xyz_out.y'left, xyz_out.y'right) after tpd; xyz_out.y <= resize(xyz_in.y + x2, xyz_out.y'left, xyz_out.y'right) after tpd;
xyz_out.z <= resize(xyz_in.z - coeff, xyz_out.z'left, xyz_out.z'right) after tpd; xyz_out.z <= resize(xyz_in.z - coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
end if; end if;
end if; end if;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/cordic_stage_post.vhd
+279 -279
View File
@@ -1,279 +1,279 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:16:14 10/02/05 -- Create Date: 12:16:14 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_stage_post - Behavioral -- Module Name: cordic_stage_post - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_stage_post is entity cordic_stage_post is
Generic Generic
( (
nbits : integer := 8; nbits : integer := 8;
nbits_frac : integer := 6; nbits_frac : integer := 6;
nbits_out : integer := 8; nbits_out : integer := 8;
nbits_frac_out : integer := 6; nbits_frac_out : integer := 6;
reg_mode : reg_mode_t := reg_mode_in reg_mode : reg_mode_t := reg_mode_in
); );
Port Port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
ce : in std_logic; ce : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
cordic_mode : in cordic_mode_t; cordic_mode : in cordic_mode_t;
ready : out std_logic; ready : out std_logic;
valid : out std_logic valid : out std_logic
); );
end cordic_stage_post; end cordic_stage_post;
architecture Behavioral of cordic_stage_post is architecture Behavioral of cordic_stage_post is
type xyz_in_t is record type xyz_in_t is record
x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
end record; end record;
type xyz_out_t is record type xyz_out_t is record
x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
end record; end record;
constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
signal xyz_in : xyz_in_t; signal xyz_in : xyz_in_t;
signal xyz_out : xyz_out_t; signal xyz_out : xyz_out_t;
signal valid_r, ready_r : std_logic; signal valid_r, ready_r : std_logic;
------------------------------------------------------------ ------------------------------------------------------------
begin begin
gen_direct: if reg_mode = none generate gen_direct: if reg_mode = none generate
reg_in : process (rst, ce, xin, yin, zin) reg_in : process (rst, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
else else
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end process; end process;
reg_out : process (rst, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
else else
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_in: if (reg_mode = reg_mode_in) generate gen_reg_in: if (reg_mode = reg_mode_in) generate
reg_in : process (rst, clk, ce, xin, yin, zin) reg_in : process (rst, clk, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
if (ce = '1') then if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end if; end if;
end process; end process;
reg_out : process (rst, ready_r, valid_r, xyz_out) reg_out : process (rst, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
else else
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_out: if (reg_mode = reg_mode_out) generate gen_reg_out: if (reg_mode = reg_mode_out) generate
reg_in : process (rst, ce, xin, yin, zin) reg_in : process (rst, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
else else
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end process; end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
if (ce = '1') then if (ce = '1') then
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_inout: if (reg_mode = reg_mode_inout) generate gen_reg_inout: if (reg_mode = reg_mode_inout) generate
reg_in : process (rst, clk, ce, xin, yin, zin) reg_in : process (rst, clk, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
if (ce = '1') then if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end if; end if;
end process; end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
if (ce = '1') then if (ce = '1') then
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
cordic_post_stage: process(xyz_in, cordic_mode) cordic_post_stage: process(xyz_in, cordic_mode)
begin begin
xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right); xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right); xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right); xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
case cordic_mode is case cordic_mode is
when cordic_mode_rotate => when cordic_mode_rotate =>
xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode); xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode);
xyz_out.y <= resize(xyz_in.y * to_sfixed(gain_tbl(nbits_out-1), xyz_in.y), xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode); xyz_out.y <= resize(xyz_in.y * to_sfixed(gain_tbl(nbits_out-1), xyz_in.y), xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode); xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode);
when cordic_mode_vector => when cordic_mode_vector =>
xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode); xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode);
xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode); xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode); xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode);
when others => null; when others => null;
end case; end case;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/cordic_stage_pre.vhd
+320 -320
View File
@@ -1,320 +1,320 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:16:14 10/02/05 -- Create Date: 12:16:14 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_stage_pre - Behavioral -- Module Name: cordic_stage_pre - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_stage_pre is entity cordic_stage_pre is
Generic Generic
( (
nbits : integer := 8; nbits : integer := 8;
nbits_frac : integer := 6; nbits_frac : integer := 6;
nbits_out : integer := 8; nbits_out : integer := 8;
nbits_frac_out : integer := 6; nbits_frac_out : integer := 6;
reg_mode : reg_mode_t := reg_mode_in reg_mode : reg_mode_t := reg_mode_in
); );
Port Port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
ce : in std_logic; ce : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
cordic_mode : in cordic_mode_t; cordic_mode : in cordic_mode_t;
ready : out std_logic; ready : out std_logic;
valid : out std_logic valid : out std_logic
); );
end cordic_stage_pre; end cordic_stage_pre;
architecture Behavioral of cordic_stage_pre is architecture Behavioral of cordic_stage_pre is
type xyz_in_t is record type xyz_in_t is record
x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
end record; end record;
type xyz_out_t is record type xyz_out_t is record
x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
end record; end record;
constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
constant pi_out_sfix : sfixed := to_sfixed(pi, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); constant pi_out_sfix : sfixed := to_sfixed(pi, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
constant pi2_out_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); constant pi2_out_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
constant pi2_in_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); constant pi2_in_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
signal xyz_in : xyz_in_t; signal xyz_in : xyz_in_t;
signal xyz_out : xyz_out_t; signal xyz_out : xyz_out_t;
signal valid_r, ready_r : std_logic; signal valid_r, ready_r : std_logic;
------------------------------------------------------------ ------------------------------------------------------------
begin begin
gen_direct: if reg_mode = none generate gen_direct: if reg_mode = none generate
reg_in : process (rst, ce, xin, yin, zin) reg_in : process (rst, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
else else
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end process; end process;
reg_out : process (rst, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
else else
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_in: if (reg_mode = reg_mode_in) generate gen_reg_in: if (reg_mode = reg_mode_in) generate
reg_in : process (rst, clk, ce, xin, yin, zin) reg_in : process (rst, clk, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
if (ce = '1') then if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end if; end if;
end process; end process;
reg_out : process (rst, ready_r, valid_r, xyz_out) reg_out : process (rst, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
else else
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_out: if (reg_mode = reg_mode_out) generate gen_reg_out: if (reg_mode = reg_mode_out) generate
reg_in : process (rst, ce, xin, yin, zin) reg_in : process (rst, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
else else
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end process; end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
if (ce = '1') then if (ce = '1') then
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
gen_reg_inout: if (reg_mode = reg_mode_inout) generate gen_reg_inout: if (reg_mode = reg_mode_inout) generate
reg_in : process (rst, clk, ce, xin, yin, zin) reg_in : process (rst, clk, ce, xin, yin, zin)
begin begin
if (rst = '1') then if (rst = '1') then
ready_r <= '0'; ready_r <= '0';
valid_r <= '0'; valid_r <= '0';
xyz_in.x <= zero_in_sfix; xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix; xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix; xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready_r <= '1'; ready_r <= '1';
valid_r <= ce; valid_r <= ce;
if (ce = '1') then if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if; end if;
end if; end if;
end process; end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin begin
if (rst = '1') then if (rst = '1') then
ready <= '0'; ready <= '0';
valid <= '0'; valid <= '0';
xout <= zero_out_sfix; xout <= zero_out_sfix;
yout <= zero_out_sfix; yout <= zero_out_sfix;
zout <= zero_out_sfix; zout <= zero_out_sfix;
elsif rising_edge(clk) then elsif rising_edge(clk) then
ready <= ready_r; ready <= ready_r;
valid <= valid_r; valid <= valid_r;
if (ce = '1') then if (ce = '1') then
xout <= xyz_out.x; xout <= xyz_out.x;
yout <= xyz_out.y; yout <= xyz_out.y;
zout <= xyz_out.z; zout <= xyz_out.z;
end if; end if;
end if; end if;
end process; end process;
end generate; end generate;
------------------------------------------------------------ ------------------------------------------------------------
cordic_proc_pre_stage: process(xyz_in, cordic_mode) cordic_proc_pre_stage: process(xyz_in, cordic_mode)
begin begin
xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right); xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right); xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right); xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
case cordic_mode is case cordic_mode is
when cordic_mode_rotate => when cordic_mode_rotate =>
if (xyz_in.z < -pi2_in_sfix) then if (xyz_in.z < -pi2_in_sfix) then
xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right); xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right); xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z + pi_out_sfix, xyz_out.z'left, xyz_out.z'right); xyz_out.z <= resize(xyz_in.z + pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
elsif (xyz_in.z > pi2_in_sfix) then elsif (xyz_in.z > pi2_in_sfix) then
xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right); xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right); xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right); xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
end if; end if;
when cordic_mode_vector => when cordic_mode_vector =>
-- if (xyz_in.x < zero_in_sfix) then -- if (xyz_in.x < zero_in_sfix) then
-- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right); -- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
-- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right); -- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
-- xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right); -- xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
-- end if; -- end if;
if (xyz_in.y < zero_in_sfix) then if (xyz_in.y < zero_in_sfix) then
xyz_out.x <= resize(-xyz_in.y, xyz_out.x'left, xyz_out.x'right); xyz_out.x <= resize(-xyz_in.y, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(xyz_in.x, xyz_out.y'left, xyz_out.y'right); xyz_out.y <= resize(xyz_in.x, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z + pi2_out_sfix, xyz_out.z'left, xyz_out.z'right); xyz_out.z <= resize(xyz_in.z + pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
else else
xyz_out.x <= resize(xyz_in.y, xyz_out.x'left, xyz_out.x'right); xyz_out.x <= resize(xyz_in.y, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(-xyz_in.x, xyz_out.y'left, xyz_out.y'right); xyz_out.y <= resize(-xyz_in.x, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z - pi2_out_sfix, xyz_out.z'left, xyz_out.z'right); xyz_out.z <= resize(xyz_in.z - pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
end if; end if;
when others => null; when others => null;
end case; end case;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
end Behavioral; end Behavioral;
-- if (y < 0) then -- if (y < 0) then
-- x' = -y -- x' = -y
-- y' = x -- y' = x
-- z' = z + pi/2; -- z' = z + pi/2;
-- else -- else
-- x' = y -- x' = y
-- y' = -x -- y' = -x
-- z' = z - pi/2; -- z' = z - pi/2;
-- end if; -- end if;
-- --
-- if (x < 0) then -- if (x < 0) then
-- x' = -x; -- x' = -x;
-- y' = -y; -- y' = -y;
-- z' = z - pi -- z' = z - pi
-- else -- else
-- x' = x; -- x' = x;
-- y' = y; -- y' = y;
-- z' = z -- z' = z
-- end if; -- end if;
lib/radio/cordic/src/cordic_top.vhd
+466 -466
View File
@@ -1,466 +1,466 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 11:52:30 10/02/05 -- Create Date: 11:52:30 10/02/05
-- Design Name: -- Design Name:
-- Module Name: cordic_top - Behavioral -- Module Name: cordic_top - Behavioral
-- Project Name: -- Project Name:
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL; use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
library ieee_proposed; library ieee_proposed;
use ieee_proposed.math_utility_pkg.all; use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_pkg.all;
library work; library work;
use work.fixed_util_pkg.all; use work.fixed_util_pkg.all;
use work.cordic_pkg.all; use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity cordic_top is entity cordic_top is
Generic Generic
( (
nbits : integer := 8; nbits : integer := 8;
nbits_frac : integer := 6; nbits_frac : integer := 6;
nbits_out : integer := 8; nbits_out : integer := 8;
nbits_frac_out : integer := 6 nbits_frac_out : integer := 6
); );
Port ( Port (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
ce : in std_logic; ce : in std_logic;
xin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); xin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
yin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); yin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
zin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); zin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
xout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); xout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
yout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); yout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
zout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); zout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
ready : out std_logic; ready : out std_logic;
valid : out std_logic; valid : out std_logic;
cordic_mode : in cordic_mode_t cordic_mode : in cordic_mode_t
); );
end cordic_top; end cordic_top;
architecture Behavioral of cordic_top is architecture Behavioral of cordic_top is
----------------------------------------------------------------------- -----------------------------------------------------------------------
COMPONENT cordic_stage_pre is COMPONENT cordic_stage_pre is
GENERIC GENERIC
( (
nbits : integer; nbits : integer;
nbits_frac : integer; nbits_frac : integer;
nbits_out : integer; nbits_out : integer;
nbits_frac_out : integer; nbits_frac_out : integer;
reg_mode : reg_mode_t reg_mode : reg_mode_t
); );
PORT PORT
( (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
ce : in std_logic; ce : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
cordic_mode : in cordic_mode_t; cordic_mode : in cordic_mode_t;
ready : OUT std_logic; ready : OUT std_logic;
valid : out std_logic valid : out std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT cordic_stage COMPONENT cordic_stage
GENERIC GENERIC
( (
nbits : integer; nbits : integer;
nbits_frac : integer; nbits_frac : integer;
nbits_out : integer; nbits_out : integer;
nbits_frac_out : integer; nbits_frac_out : integer;
reg_mode : reg_mode_t reg_mode : reg_mode_t
); );
PORT( PORT(
rst : IN std_logic; rst : IN std_logic;
clk : IN std_logic; clk : IN std_logic;
ce : IN std_logic; ce : IN std_logic;
xin : IN sfixed; xin : IN sfixed;
yin : IN sfixed; yin : IN sfixed;
zin : IN sfixed; zin : IN sfixed;
xout : OUT sfixed; xout : OUT sfixed;
yout : OUT sfixed; yout : OUT sfixed;
zout : OUT sfixed; zout : OUT sfixed;
coeff : in sfixed; coeff : in sfixed;
dir_cw : in std_logic; dir_cw : in std_logic;
stage_count : IN integer; stage_count : IN integer;
cordic_mode : in cordic_mode_t; cordic_mode : in cordic_mode_t;
ready : OUT std_logic; ready : OUT std_logic;
valid : out std_logic valid : out std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT cordic_stage_post is COMPONENT cordic_stage_post is
GENERIC GENERIC
( (
nbits : integer; nbits : integer;
nbits_frac : integer; nbits_frac : integer;
nbits_out : integer; nbits_out : integer;
nbits_frac_out : integer; nbits_frac_out : integer;
reg_mode : reg_mode_t reg_mode : reg_mode_t
); );
PORT PORT
( (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
ce : in std_logic; ce : in std_logic;
xin : in sfixed; xin : in sfixed;
yin : in sfixed; yin : in sfixed;
zin : in sfixed; zin : in sfixed;
xout : out sfixed; xout : out sfixed;
yout : out sfixed; yout : out sfixed;
zout : out sfixed; zout : out sfixed;
cordic_mode : in cordic_mode_t; cordic_mode : in cordic_mode_t;
ready : OUT std_logic; ready : OUT std_logic;
valid : out std_logic valid : out std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT rom_arctan is COMPONENT rom_arctan is
GENERIC GENERIC
( (
nbits : integer := 8; nbits : integer := 8;
nbits_frac : integer := 8 nbits_frac : integer := 8
); );
PORT PORT
( (
addr : in unsigned(6 downto 0); addr : in unsigned(6 downto 0);
dout : out sfixed dout : out sfixed
); );
END COMPONENT; END COMPONENT;
----------------------------------------------------------------------- -----------------------------------------------------------------------
type state_type is (st_input, st_ready, st_pre_stage_in, st_pre_stage_out, st_proc_stage_in, st_proc_stage_out, st_post_stage_in, st_post_stage_out); type state_type is (st_input, st_ready, st_pre_stage_in, st_pre_stage_out, st_proc_stage_in, st_proc_stage_out, st_post_stage_in, st_post_stage_out);
constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-- Define number of LSB guard bits -- Define number of LSB guard bits
constant guard_nbits : integer := integer(log2(real(nbits))+0.5); constant guard_nbits : integer := integer(log2(real(nbits))+0.5);
-- Define number of internal stage bits -- Define number of internal stage bits
constant stage_nbits : integer := nbits + guard_nbits; -- add more internal precision constant stage_nbits : integer := nbits + guard_nbits; -- add more internal precision
constant stage_nbits_frac : integer := nbits_frac; constant stage_nbits_frac : integer := nbits_frac;
-- Set number of coefficient bits -- Set number of coefficient bits
constant coeff_nbits : integer := nbits; constant coeff_nbits : integer := nbits;
constant coeff_nbits_frac : integer := nbits; -- coeffs have no integer part constant coeff_nbits_frac : integer := nbits; -- coeffs have no integer part
-- Set number of iteration with respect to bit size -- Set number of iteration with respect to bit size
constant max_stage_count : integer := stage_nbits; constant max_stage_count : integer := stage_nbits;
-- INPUT -- INPUT
-- Input pre stage -- Input pre stage
signal pre_stage_en : std_logic; signal pre_stage_en : std_logic;
signal xin_pre, yin_pre, zin_pre : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); signal xin_pre, yin_pre, zin_pre : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-- Output pre stage -- Output pre stage
signal pre_stage_ready, pre_stage_valid : std_logic; signal pre_stage_ready, pre_stage_valid : std_logic;
signal xout_pre, yout_pre, zout_pre : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); signal xout_pre, yout_pre, zout_pre : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Input processing stage -- Input processing stage
signal proc_stage_en: std_logic; signal proc_stage_en: std_logic;
signal xin_stage, yin_stage, zin_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); signal xin_stage, yin_stage, zin_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Output processing stage -- Output processing stage
signal proc_stage_ready, proc_stage_valid : std_logic; signal proc_stage_ready, proc_stage_valid : std_logic;
signal xout_stage, yout_stage, zout_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); signal xout_stage, yout_stage, zout_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Input post stage -- Input post stage
signal post_stage_en : std_logic; signal post_stage_en : std_logic;
signal xin_post, yin_post, zin_post : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); signal xin_post, yin_post, zin_post : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Output post stage -- Output post stage
signal post_stage_ready, post_stage_valid : std_logic; signal post_stage_ready, post_stage_valid : std_logic;
signal xout_post, yout_post, zout_post : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); signal xout_post, yout_post, zout_post : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-- ROM -- ROM
signal rom_addr : unsigned (6 downto 0); signal rom_addr : unsigned (6 downto 0);
signal rom_data : sfixed(sproto(coeff_nbits, coeff_nbits_frac)'high downto sproto(coeff_nbits, coeff_nbits_frac)'low); signal rom_data : sfixed(sproto(coeff_nbits, coeff_nbits_frac)'high downto sproto(coeff_nbits, coeff_nbits_frac)'low);
-- Misc. -- Misc.
signal state, next_state : state_type; signal state, next_state : state_type;
signal count : integer range 0 to max_stage_count-1 := 0; signal count : integer range 0 to max_stage_count-1 := 0;
signal count_en, dir_cw, valid_s : std_logic; signal count_en, dir_cw, valid_s : std_logic;
begin begin
----------------------------------------------------------------------- -----------------------------------------------------------------------
cordic_proc_mode : process(rst, zin_stage, yin_stage, cordic_mode) cordic_proc_mode : process(rst, zin_stage, yin_stage, cordic_mode)
begin begin
if (rst = '1') then if (rst = '1') then
dir_cw <= '0'; dir_cw <= '0';
else else
dir_cw <= '0'; dir_cw <= '0';
case cordic_mode is case cordic_mode is
when cordic_mode_rotate => when cordic_mode_rotate =>
if (zin_stage(zin_stage'high) = '1') then if (zin_stage(zin_stage'high) = '1') then
dir_cw <= '1'; dir_cw <= '1';
end if; end if;
when cordic_mode_vector => when cordic_mode_vector =>
if (yin_stage(yin_stage'high) = '1') then if (yin_stage(yin_stage'high) = '1') then
dir_cw <= '0'; dir_cw <= '0';
else else
dir_cw <= '1'; dir_cw <= '1';
end if; end if;
when others => null; when others => null;
end case; end case;
end if; end if;
end process; end process;
----------------------------------------------------------------------- -----------------------------------------------------------------------
counter: process (clk, rst, count, count_en) counter: process (clk, rst, count, count_en)
begin begin
if (rst = '1') then if (rst = '1') then
count <= 0; count <= 0;
rom_addr <= (others => '0'); rom_addr <= (others => '0');
else else
if (clk'event and clk = '1') then if (clk'event and clk = '1') then
rom_addr <= to_unsigned(count, rom_addr'length); rom_addr <= to_unsigned(count, rom_addr'length);
if (count_en = '1' and count < max_stage_count-1) then if (count_en = '1' and count < max_stage_count-1) then
count <= count + 1 after tpd; count <= count + 1 after tpd;
else else
count <= 0; count <= 0;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
----------------------------------------------------------------------- -----------------------------------------------------------------------
OUTPUT_PROC: process (clk, rst, state, xout_stage, yout_stage, zout_stage) OUTPUT_PROC: process (clk, rst, state, xout_stage, yout_stage, zout_stage)
begin begin
if (rst='1') then if (rst='1') then
valid <= '0'; valid <= '0';
xout <= zero_sfix after tpd; xout <= zero_sfix after tpd;
yout <= zero_sfix after tpd; yout <= zero_sfix after tpd;
zout <= zero_sfix after tpd; zout <= zero_sfix after tpd;
-- assign other outputs to reset value -- assign other outputs to reset value
elsif (clk'event and clk = '1') then elsif (clk'event and clk = '1') then
valid <= '0'; valid <= '0';
if(post_stage_valid = '1') then if(post_stage_valid = '1') then
xout <= xout_post; xout <= xout_post;
yout <= yout_post; yout <= yout_post;
zout <= zout_post; zout <= zout_post;
valid <= '1'; valid <= '1';
end if; end if;
end if; end if;
end process; end process;
----------------------------------------------------------------------- -----------------------------------------------------------------------
--Insert the following in the architecture after the begin keyword --Insert the following in the architecture after the begin keyword
FSM_PROC: process (clk, rst, xout_stage, yout_stage, zout_stage) FSM_PROC: process (clk, rst, xout_stage, yout_stage, zout_stage)
begin begin
if (rst='1') then if (rst='1') then
state <= st_ready; state <= st_ready;
-- assign other outputs to reset value -- assign other outputs to reset value
elsif (clk'event and clk = '1') then elsif (clk'event and clk = '1') then
state <= next_state after tpd; state <= next_state after tpd;
-- assign other outputs to internal signals -- assign other outputs to internal signals
end if; end if;
end process; end process;
--MOORE State Machine - Outputs based on state only --MOORE State Machine - Outputs based on state only
Control_proc: process (state, xin, yin, zin, xout_pre, yout_pre, zout_pre, xout_stage, yout_stage, zout_stage) Control_proc: process (state, xin, yin, zin, xout_pre, yout_pre, zout_pre, xout_stage, yout_stage, zout_stage)
begin begin
--insert statements to decode internal output signals --insert statements to decode internal output signals
--below is simple example --below is simple example
ready <= '0'; ready <= '0';
valid_s <= '0'; valid_s <= '0';
count_en <= '0'; count_en <= '0';
pre_stage_en <= '0'; pre_stage_en <= '0';
proc_stage_en <= '0'; proc_stage_en <= '0';
post_stage_en <= '0'; post_stage_en <= '0';
xin_pre <= xin; xin_pre <= xin;
yin_pre <= yin; yin_pre <= yin;
zin_pre <= zin; zin_pre <= zin;
xin_stage <= xout_stage; xin_stage <= xout_stage;
yin_stage <= yout_stage; yin_stage <= yout_stage;
zin_stage <= zout_stage; zin_stage <= zout_stage;
xin_post <= xout_stage; xin_post <= xout_stage;
yin_post <= yout_stage; yin_post <= yout_stage;
zin_post <= zout_stage; zin_post <= zout_stage;
case (state) is case (state) is
when st_ready => when st_ready =>
ready <= '1'; ready <= '1';
when st_pre_stage_in => when st_pre_stage_in =>
pre_stage_en <= '1'; pre_stage_en <= '1';
when st_pre_stage_out => when st_pre_stage_out =>
count_en <= '1'; count_en <= '1';
proc_stage_en <= '1'; proc_stage_en <= '1';
xin_stage <= xout_pre; xin_stage <= xout_pre;
yin_stage <= yout_pre; yin_stage <= yout_pre;
zin_stage <= zout_pre; zin_stage <= zout_pre;
when st_proc_stage_in => when st_proc_stage_in =>
count_en <= '1'; count_en <= '1';
proc_stage_en <= '1'; proc_stage_en <= '1';
when st_post_stage_in => when st_post_stage_in =>
post_stage_en <= '1'; post_stage_en <= '1';
when others => when others =>
end case; end case;
end process; end process;
NEXT_STATE_DECODE: process (state, ce, count) NEXT_STATE_DECODE: process (state, ce, count)
begin begin
--declare default state for next_state to avoid latches --declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state next_state <= state; --default is to stay in current state
--insert statements to decode next_state --insert statements to decode next_state
--below is a simple example --below is a simple example
case (state) is case (state) is
when st_ready => when st_ready =>
if ce = '1' then if ce = '1' then
next_state <= st_input; next_state <= st_input;
end if; end if;
when st_input => when st_input =>
if ce = '0' then if ce = '0' then
next_state <= st_pre_stage_in; next_state <= st_pre_stage_in;
end if; end if;
when st_pre_stage_in => when st_pre_stage_in =>
next_state <= st_pre_stage_out; next_state <= st_pre_stage_out;
when st_pre_stage_out => when st_pre_stage_out =>
next_state <= st_proc_stage_in; next_state <= st_proc_stage_in;
when st_proc_stage_in => when st_proc_stage_in =>
if (count = max_stage_count-2) then if (count = max_stage_count-2) then
next_state <= st_post_stage_in; next_state <= st_post_stage_in;
end if; end if;
when st_post_stage_in => when st_post_stage_in =>
next_state <= st_ready; next_state <= st_ready;
when others => when others =>
next_state <= st_ready; next_state <= st_ready;
end case; end case;
end process; end process;
----------------------------------------------------------------------- -----------------------------------------------------------------------
Inst_cordic_stage_pre: cordic_stage_pre Inst_cordic_stage_pre: cordic_stage_pre
GENERIC MAP GENERIC MAP
( (
nbits => nbits, nbits => nbits,
nbits_frac => nbits_frac, nbits_frac => nbits_frac,
nbits_out => stage_nbits, nbits_out => stage_nbits,
nbits_frac_out => stage_nbits_frac, nbits_frac_out => stage_nbits_frac,
reg_mode => reg_mode_in reg_mode => reg_mode_in
) )
PORT MAP PORT MAP
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
ce => pre_stage_en, ce => pre_stage_en,
xin => xin_pre, xin => xin_pre,
yin => yin_pre, yin => yin_pre,
zin => zin_pre, zin => zin_pre,
xout => xout_pre, xout => xout_pre,
yout => yout_pre, yout => yout_pre,
zout => zout_pre, zout => zout_pre,
ready => pre_stage_ready, ready => pre_stage_ready,
valid => pre_stage_valid, valid => pre_stage_valid,
cordic_mode => cordic_mode cordic_mode => cordic_mode
); );
Inst_cordic_stage: cordic_stage Inst_cordic_stage: cordic_stage
GENERIC MAP GENERIC MAP
( (
nbits => stage_nbits, nbits => stage_nbits,
nbits_frac => stage_nbits_frac, nbits_frac => stage_nbits_frac,
nbits_out => stage_nbits, nbits_out => stage_nbits,
nbits_frac_out => stage_nbits_frac, nbits_frac_out => stage_nbits_frac,
reg_mode => reg_mode_in reg_mode => reg_mode_in
) )
PORT MAP PORT MAP
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
ce => proc_stage_en, ce => proc_stage_en,
xin => xin_stage, xin => xin_stage,
yin => yin_stage, yin => yin_stage,
zin => zin_stage, zin => zin_stage,
xout => xout_stage, xout => xout_stage,
yout => yout_stage, yout => yout_stage,
zout => zout_stage, zout => zout_stage,
coeff => rom_data, coeff => rom_data,
dir_cw => dir_cw, dir_cw => dir_cw,
stage_count => count, stage_count => count,
ready => proc_stage_ready, ready => proc_stage_ready,
valid => proc_stage_valid, valid => proc_stage_valid,
cordic_mode => cordic_mode cordic_mode => cordic_mode
); );
Inst_cordic_stage_post: cordic_stage_post Inst_cordic_stage_post: cordic_stage_post
GENERIC MAP GENERIC MAP
( (
nbits => stage_nbits, nbits => stage_nbits,
nbits_frac => stage_nbits_frac, nbits_frac => stage_nbits_frac,
nbits_out => nbits_out, nbits_out => nbits_out,
nbits_frac_out => nbits_frac_out, nbits_frac_out => nbits_frac_out,
reg_mode => reg_mode_in reg_mode => reg_mode_in
) )
PORT MAP PORT MAP
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
ce => post_stage_en, ce => post_stage_en,
xin => xin_post, xin => xin_post,
yin => yin_post, yin => yin_post,
zin => zin_post, zin => zin_post,
xout => xout_post, xout => xout_post,
yout => yout_post, yout => yout_post,
zout => zout_post, zout => zout_post,
ready => post_stage_ready, ready => post_stage_ready,
valid => post_stage_valid, valid => post_stage_valid,
cordic_mode => cordic_mode cordic_mode => cordic_mode
); );
Inst_rom_arctan: rom_arctan Inst_rom_arctan: rom_arctan
GENERIC MAP GENERIC MAP
( (
nbits => coeff_nbits, nbits => coeff_nbits,
nbits_frac => coeff_nbits_frac nbits_frac => coeff_nbits_frac
) )
PORT MAP PORT MAP
( (
addr => rom_addr, addr => rom_addr,
dout => rom_data dout => rom_data
); );
-------------------------------------------------------------------- --------------------------------------------------------------------
end Behavioral; end Behavioral;
lib/radio/cordic/src/tb_cordic_pipe_top.vhd
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lib/radio/cordic/src/tb_cordic_top.vhd
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