- fixed some bugs
git-svn-id: http://moon:8086/svn/vhdl/trunk@128 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -12,4 +12,4 @@ view wave
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view structure
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view signals
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run 5000us
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run 8ms
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@@ -6,15 +6,15 @@ add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
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add wave -noupdate -format Logic /tb_mips_muldiv/start
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add wave -noupdate -format Logic /tb_mips_muldiv/busy
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add wave -noupdate -format Logic /tb_mips_muldiv/s_un
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
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add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
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add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result
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add wave -noupdate -format Logic /tb_mips_muldiv/check
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add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
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add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
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add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
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@@ -61,7 +61,7 @@ add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
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add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
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add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {102205454 ps} 0}
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WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0}
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configure wave -namecolwidth 149
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configure wave -valuecolwidth 171
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configure wave -justifyvalue left
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@@ -75,4 +75,4 @@ configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {102150244 ps} {102363615 ps}
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WaveRestoreZoom {0 ps} {8400 us}
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@@ -63,12 +63,14 @@ ARCHITECTURE behavior OF tb_mips_muldiv IS
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signal start : std_logic := '0';
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signal din_hi : word_t := (others => '-');
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signal din_lo : word_t := (others => '-');
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signal ref_hi : word_t := (others => '-');
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signal ref_lo : word_t := (others => '-');
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signal dout : word_t;
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signal hilo_sel : std_logic := '0';
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signal result : unsigned (2*word_t'length-1 downto 0);
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signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0');
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signal ref_result : unsigned (2*word_t'length-1 downto 0);
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signal ref_hi : unsigned (word_t'length-1 downto 0);
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signal rtmp : unsigned (2*word_t'length-1 downto 0);
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signal tmp2 : unsigned (word_t'length-1 downto 0);
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signal check : std_logic;
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type word_array_t is array (natural range <>) of word_t;
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@@ -164,35 +166,31 @@ CLK_GEN: process
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end process;
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REF_GEN: process
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variable tmp : unsigned (2*word_t'length-1 downto 0);
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variable tmp2 : unsigned (word_t'length-1 downto 0);
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begin
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if mul_divn = '0' then
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wait until rising_edge(clk) and start = '1';
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ref_lo <= din_lo;
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ref_hi <= din_hi;
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wait until rising_edge(clk) and busy = '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk) and check = '1';
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if s_un = '1' then
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tmp := unsigned(signed(result(31 downto 0)) * signed(ref_lo));
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tmp2 := unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32)));
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ref_result <= X"00000000" & tmp2(31 downto 0);
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rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
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wait until rising_edge(clk);
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tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
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wait until rising_edge(clk);
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ref_hi <= tmp2(31 downto 0);
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else
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tmp := result(31 downto 0) * ref_lo;
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tmp2 := tmp(31 downto 0) + result(63 downto 32);
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ref_result <= X"00000000" & tmp2(31 downto 0);
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rtmp <= md_result(31 downto 0) * din_lo;
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wait until rising_edge(clk);
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tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32);
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wait until rising_edge(clk);
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ref_hi <= tmp2(31 downto 0);
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end if;
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wait until rising_edge(clk);
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if ref_lo /= X"00000000" then
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if din_lo /= X"00000000" then
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if ENABLE_FAIL_REPORT then
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assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure;
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assert din_hi = ref_hi report "Error on divison" severity failure;
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end if;
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end if;
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else
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wait until rising_edge(clk) and start = '1';
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wait until rising_edge(clk) and busy = '0';
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wait until rising_edge(clk) and check = '1';
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if s_un = '1' then
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ref_result <= unsigned(signed(din_hi) * signed(din_lo));
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else
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@@ -202,7 +200,7 @@ REF_GEN: process
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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if ENABLE_FAIL_REPORT then
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assert ref_result = result report "Error on multiplication" severity failure;
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assert ref_result = md_result report "Error on multiplication" severity failure;
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end if;
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end if;
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@@ -221,6 +219,7 @@ STIMULUS: process
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s_un <= '0';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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@@ -231,17 +230,23 @@ STIMULUS: process
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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result(63 downto 32) <= dout;
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wait for 2*CLK_PERIOD;
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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s_un <= '1';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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@@ -252,11 +257,16 @@ STIMULUS: process
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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result(63 downto 32) <= dout;
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wait for 2*CLK_PERIOD;
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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@@ -264,6 +274,7 @@ STIMULUS: process
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s_un <= '0';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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@@ -274,16 +285,23 @@ STIMULUS: process
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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result(63 downto 32) <= dout;
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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s_un <= '1';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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@@ -294,10 +312,16 @@ STIMULUS: process
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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result(63 downto 32) <= dout;
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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